Open dmitry-salin opened 1 month ago
@dmitry-salin do these intrinsics compose with nvvm synchronization primitives or are they only for CPU?
Seems like nvvm does not support atomic load/store https://docs.nvidia.com/cuda/nvvm-ir-spec/#atomic-memory-ordering-constraints
Still, this would be very useful for implementing CPU locking/async/concurrent primitives
@dmitry-salin do these intrinsics compose with nvvm synchronization primitives or are they only for CPU?
Seems like nvvm does not support atomic load/store https://docs.nvidia.com/cuda/nvvm-ir-spec/#atomic-memory-ordering-constraints
Still, this would be very useful for implementing CPU locking/async/concurrent primitives
I don't know much about nvvm, but it looks like MLIR's LLVM dialect is CPU-only.
Review Mojo's priorities
What is your request?
There is already
__mlir_op.pop.load[alignment](address)
, but it only hasalignment
attribute. We needordering
::mlir::LLVM::AtomicOrderingAttr and possibly other additional attributes - https://mlir.llvm.org/docs/Dialects/LLVM/#attributes-31 The same applies to__mlir_op.pop.store[alignment](value, address)
. Thefence
is currently missing - https://mlir.llvm.org/docs/Dialects/LLVM/#llvmfence-llvmfenceopWhat is your motivation for this change?
Mojo, as a systems programming language, requires basic atomic instructions.
Any other details?
No response