mohandev2
commented
13 years ago I wonder if it can be implemented with existing instrument or with set of existing instruments. Seems the idea is very specific. And a new HPI instrument shall be generic one.
Original comment by: avpak
Proposal: Support telco clock synchronization
HPI should support a new type of management instrument for telecom clock synchronization (Phase-Locked Loop Synchronization). Since HPI evolution in SA Forum seems pretty dormant, NSN would like to ask for support by OpenHPI with the proposal to introduce new interfaces to make the management of telco clock synchronization independent of the hardware.
Introduction
Synchronous Telco systems distribute timing information that is derived from an extremely accurate central system clock. Usually such central systems clocks select their synchronization input from a variety of primary reference sources (PRS) offered. Individual PRS can be used as applicable input signal to different level in a multi-tier PLL synchronization architecture as depicted in figure 1. Here the lower tier PLLs feed a derived clock signal into the system as input for next higher tier PLLs (central PLL) or to other PLLs in the same tier if the next higher tier is not provided or is otherwise somehow unavailable.
Central systems clock generators within synchronous telecommunication systems usually are located on a specific timing card that houses a central digital phase-lock loop (PLL) device that is capable of meeting the required timing and synchronization standards defined by ITU-T, ANSI and Telcordia. Most systems will even provide two redundant timing cards (with master/slave PLL functionality) to ensure reliable, uninterrupted synchronization throughout the system. Once the central (master) PLL has selected its primary reference source it will drive the backplane with a clock and frame pulse (T0, T04) to be used by all the line cards in the system. This is for example standard in ATCA systems where the backplane specification requires tight phase alignment between the system clocks.
The central PLL can be configured to select a BITS/SSU synchronization source T3 for use in external synchronization mode or it may select one of the other derived PRS signals internally from the backplane (e.g. T1/T2 via CLK3A/B backplane bus), In a redundant system the timing card may also be required to select the backplane systems clocks from the other timing card. The master (or active) timing card selects one of the network references (line timed or externally timed). The resource that holds the slave (redundant) central PLL selects the master system clocks and closely tracks these clocks to provide redundant system clocks that are both frequency and phase aligned to the master. In the case of a failure on the master timing card, the slave timing card assumes the role of master. PLLs can be commanded into ACTIVE, INACTIVE or OFF state upon user demand. When the PLL is in a non-ACTIVE state it will not output any internal PLL synchronization signals. In case of central PLLs the master PLL is in ACTIVE state while the slave PLL resides in INACTIVE state
Idea:
OpenHPI should introduce a new type of management instrument, I call it here PSMI (PLL Synchronization Management Instrument). This would need an extension of the set of RDR types, capabilities etc.
For the PSMI, there would be a new resource type, a few functions and also a new event type.
New functions:
- PLLPrimaryReferenceSourceInfoGet
This function gets all parameters of all primary reference sources currently configured for a resource that provides a PSMI.
- PLLPrimaryReferenceSourceSet
This function is used to configure all parameters related to external primary reference sources applicable for usage by the specified target PLL resource. Different external reference source information can be assigned to a PSMI by way of a user defined list. This function can also be used to command the PSMI to select or deselect a specific PRS from that list of different reference sources for system PLL synchronization.
- saHpiPLLSynchronizationStatusGet() This function allows an HPI User to request a specified PSMI on a timing resource to provide the current PLL synchronization status information. The user is informed about the PLL state, PLL operating mode and the selected primary reference source used for synchronization.
- PLLSynchronizationStateSet
This function allows an HPI User to request a PSMI on a timing capable resource to set a PLL into a specified state and thus role in the chain of synchronization hierarchies within the system. This API enables the HPI user to transition a PLL into the active, inactive or off state. When the PLL is set into a non-active state it shall stop any synchronization signal output. In case of PLL redundancy setting an active PLL into a non-active state can initiate an automatic switchover of the master role
New Event:
Unsolicited PSMI events are issued by PSMI implementations when the synchronization status of a Phase-Locked Loop timing device or a Primary Reverence Source selection changes. These events are associated with specific PLL Synchronization management instruments, provides the following information - PLL state (active, inactive, off) - PLL operating mode (off, slave, locked, holdover, ree-running) - PRS selected at time of reporting - PRS previously used The event reason code can indicate: - one or more PRS signals selected are lost or our-of-frequency, - lock failure, - synchronization regain, - PRS reselection.
Reported by: ulikleber
Original Ticket: openhpi/feature-requests/637