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monotech / MOS_CPU_Replacer

MOS CPU Replacer – replace rare/expensive/unreliable MOS CPUs
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High Impedance On Data Bus #4

Open ewsz opened 1 year ago

ewsz commented 1 year ago

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monotech commented 1 year ago

Cheers, glad you like the project! Yea it would be nice to iron out any remaining compatibility issues.

Sorry, I have a little confusion when reading your message due to polarity naming. In my schematic, I have named the 6510 pin "/AEC". Later in the schematic, there exists an inverted version of this called "AEC".

At present, the device's D0-7 bus goes high-impedance when /AEC goes low. When /AEC goes high, The D0-7 bus transceiver becomes active, unless the current address is 0000 or 0001.

Are you suggesting I should control the D0-7 bus transceiver with AEC (that's inverted /AEC) alone? That could simplify things slightly. I am not really sure about the architectures of these machines, and how the C16 differs.

Unfortunately, the 6510 datasheet and related same-die chip datasheets, seem incomplete or rough. The purpose of the AEC pin is different in the 6510 datasheet compared to the 7501 and 8502 datasheets (6510T datasheet is missing).

monotech commented 1 year ago

Thanks for the info!

The first document you linked, states that the AEC pin on a 7501 affects the address bus. It doesn't mention data bus or RW line like the 6510 datasheet.

In my design, Gate-in latches the RW output for 7501. Latching is different to setting RW high (unless in all practical use cases Gate-in is only being asserted when RW is currently high). Perhaps this is a mistake. I don't own any TED systems at the moment to test unfortunately.

I have just updated the files to Rev2, which includes a small change (only affects 6510 and 6510T).

Regarding 6510T, this config is still untested, as I don't have a 1551. I can see how this board would be overkill for that. Due to the low demand for 6510T, I won't bother making a simplified version in this case.

Cheers!