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mortbopet / VSRTL

Visual Simulation of Register Transfer Logic
MIT License
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Circuit simulation visualization ideas #12

Open mortbopet opened 5 years ago

mortbopet commented 5 years ago

This issue is intended for tracking a discussion on suggestions for features which improve the visualization of a circuit during simulation.

mortbopet commented 5 years ago

fb7c17f0053a53fccd introduces animation of ports which are not boolean signals, by quickly blinking them when their value changes.

mars4zhu commented 5 years ago

How about using with iverilog(the famous open source verilog simulator and synthesis tools ), with the vvp intermediate output of iverilog, we can visualize nearly every verilog source code.....

This is my idea of VSRTL.

mortbopet commented 5 years ago

Definitely seems like a good idea to leverage a project which takes care of parsing the HDL language. Are you suggesting that for VSRTL, a parser for the vvp intermediate representation should be written, which may use the VSRTL Core-based simulation engine (and circuit representation), or that the iverilog vvp simulator is to replace the simulation logic currently available in VSRTL, and (somehow, not sure about how viable this would be) a visual representation of the circuit could be generation from hooking into the vvp simulator.

Glansing over the file format of vvp IR (https://github.com/steveicarus/iverilog/tree/master/vvp), i am unsure about how much information is contained within which directly corresponds to RTL primitives (Ie. multiplexers, logic gates etc.). It would be information like this which the VSRTL Core circuit would be based upon, for the Graphics library to be able to generate the accompanying visualization of these objects.

Do you have any other good resources or experiences with the project? i have not worked with iverilog before.