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mortbopet / VSRTL

Visual Simulation of Register Transfer Logic
MIT License
89 stars 18 forks source link

Do not explore entire graph for each clock cycle #40

Closed mortbopet closed 5 years ago

mortbopet commented 5 years ago

Currently, the entire graph is explored for each clock cycle, to ensure correctness. However, this exploration in terms of properly sequencing the propagation operations is only required once.

This task should

  1. save the result from the exploration into a stack of components which needs to be propagated
  2. use this stack for all future clockings

Relates to: #9

mortbopet commented 5 years ago

Already done, the design creates a propagationstack, which is the sequence of ports to be updated.