SPComputer, which adds a register to hold SP, making push/pop machine instructions. This adds a lot of complexity to decoding the instruction, but saves a lot of cycles, and a fair amount of ROM.
ThreadedComputer, which adds a register to hold a return address, and CALL/RTN instructions making it very cheap to jump in and out of a library of opcode handlers. That saves a ton of ROM, allowing very large programs to be translated, but takes more cycles to run them.
Each one is implemented in a single module with new CPU and Computer components, a new VM translator, and a main function that can run programs interactively, as well as printing the generated assembly for inspection.
Some adjustments were made to tests to accommodate varying implementations:
Avoid RAM[0] in the simple early tests
Define an accessor for sp in the common wrapper for Computer, so it can be overridden to use the register when needed.
This is where it gets interesting.
Two new CPUs are implemented:
SPComputer, which adds a register to holdSP, making push/pop machine instructions. This adds a lot of complexity to decoding the instruction, but saves a lot of cycles, and a fair amount of ROM.ThreadedComputer, which adds a register to hold a return address, and CALL/RTN instructions making it very cheap to jump in and out of a library of opcode handlers. That saves a ton of ROM, allowing very large programs to be translated, but takes more cycles to run them.Each one is implemented in a single module with new CPU and Computer components, a new VM translator, and a
mainfunction that can run programs interactively, as well as printing the generated assembly for inspection.Some adjustments were made to tests to accommodate varying implementations:
spin the common wrapper for Computer, so it can be overridden to use the register when needed.