Memory should model read latency

The current implementation of memory for simulation is unrealistic in that it provides "immediate" access to data; as soon as the address is applied to the input, the content word can be read from the output as if there were no inherent latency.

Part of the rationale for making memory a separate component for simulation is that real chips tend to use a higher-density technology for memory, so simulating a memory built from logic gates is silly. But to keep some level of realism, we shouldn't actually let chip designers treat the memory like a register that you can access within a single cycle. The latency of accessing memory should be a design constraint (i.e. if you want to make your chip go faster by having more accessible data, you have to add gates for registers, you can't cheat by treating the memory like a magic cache that provides sub-cycle access.)

In fact, most of the designs implicitly tolerate one-cycle memory latency; they're designed to do address calculation with one instruction and then consume the value from memory with the next. But the simulator doesn't model that behavior and some of the alternative designs I've added are probably playing fast and loose. In particular, I have a non-pipelined RiSC-16 implementation which uses this cheat (or I think it does; it would be great if the simulation proved it.)

Requirements:

RAM updates its output only on the cycle after a (new) address is presented
Accept a new address in each cycle, so throughput is still one word per cycle, just with a delay/latch
Document/test that behavior so solutions are still consistent with the discrete component

What, if anything, does this mean for writes? If there's write delay, can it be observed? It's OK to set the address, the input word, and the load bit all in the same cycle. If you then unset load and try to read the same word, that would be subject to the normal read delay, right?

Well, this wasn't as simple as I thought:

Even the "standard" CPU now has to do some "pipelining"; values that are going to be written to A have to be forwarded to the address bus. That's probably too tricky for beginners.
Not only reads, but also writes have to operate on the latched address, so that the standard CPU can do things like M=M-1. Experience debugging it shows that write latency is even more confusing than read latency to think about.

To be clear, I'm claiming that a single-cycle read-write to the same address is still "realistic" because the RAM only has to address one cell (and the bus only has to move one address). Anyway it seems to be unavoidable; logic to stall the simple CPU to wait for memory is more than I want to ask for.

mossprescott / pynand

Memory should model read latency #34