What steps will reproduce the problem?
1. Run the spirom test
What is the expected output? What do you see instead?
There is a delay (10ms) in the spirom_cycle, this is causing long write
cylces. The issue was that the FC (frame complete) flag in SR1 is cleared
when SR1 is read. A provious read of the SR1 reg was clearing this bit
cuasing the while loop poll of this bit to lock up and the need to add the
dalay.
What version of the product are you using? On what operating system?
Rev b
Please provide any additional information below.
Fixed file is attached. Please validate.
Original issue reported on code.google.com by t-c...@live.co.uk on 1 Nov 2009 at 9:22
Original issue reported on code.google.com by
t-c...@live.co.uk
on 1 Nov 2009 at 9:22Attachments: