Cache misses (much) worse for page-aligned (e.g. power of two) accesses

mratsim / weave

A state-of-the-art multithreading runtime: message-passing based, fast, scalable, ultra-low overhead

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Cache misses (much) worse for page-aligned (e.g. power of two) accesses #176

Closed dumblob closed 2 years ago

dumblob commented 2 years ago

Sorry for spam, but I thought that the community around weave could be interested in the following "paradox" showing real measurements about rather huge negative impact of page-aligned access under certain conditions on x86. Bare with me if you knew about this :wink:.

https://danluu.com/3c-conflict/