mrehkopf
commented
8 years ago I wouldn't say this is generally impossible, though it might be impossible to reach 100% compatibility. Using the 65816 emulation mode should work in most cases unless a game uses 6502 illegal opcodes. APU can be emulated by the FPGA and output directly via the sd2snes DAC (normally used for MSU1 audio) so that is out of the way. The trickiest part is getting any picture out of the system. When using the FPGA to emulate a NES PPU and render the picture, the SNES data bus bandwidth becomes the bottleneck. It is impossible to stream a NES resolution picture to VRAM at 60fps. Alternatively the FPGA could provide a sort of compatibility layer, acting as a PPU to NES code but translating the PPU state so it becomes usable by the S-PPU which is in turn used to render the picture. In this case it would be necessary to periodically interrupt the CPU to update sprite tables, possibly preload some HDMA tables for the upcoming frame (if realtime updates turn out infeasible), map the rest of the registers accordingly etc. I do not know enough about the NES architecture to answer this thoroughly right now, though ;) Controllers should "just work" because of the compatible $4016/4017 registers.
ramapcsx2
eadmaster
juef17
A software solution for this was discussed some years ago in this forum.
Btw recently many NES implementations in FPGA came up, so it may possible to reuse some of their code and add NES backward-compatibility by emulating the missing chips in hardware.
I am not sure if it is doable, but considering the vast library of NES titles this could be interesting for many users and worth the effort IMO.
To save space on the FPGA, the main SNES RAM and CPU could be used in backward-compatibility mode.