mshr-h / vscode-systemverilog-support

[deprecated]use mshr-h/vscode-verilog-hdl-support
https://github.com/mshr-h/vscode-verilog-hdl-support
MIT License
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Alignment of ports adds semicolons to end #32

Open bjaminn opened 6 years ago

bjaminn commented 6 years ago

When aligning the ports of a module, the end of line gets semicolons added.

  input  logic clk,

  input  logic we_n,
  input  logic cas_n,
  input  logic ras_n,
  input  logic cs_n,

  output logic       clk_div,

  output logic [7:0] we_n_gd,
  output logic [7:0] cas_n_gd,
  output logic [7:0] ras_n_gd,
  output logic [7:0] cs_n_gd

becomes

  logic       input clk,          ; 

  logic       input we_n,         ; 
  logic       input cas_n,        ; 
  logic       input ras_n,        ; 
  logic       input cs_n,         ; 

  logic       output clk_div,     ; 

  logic [7:0] output we_n_gd,     ; 
  logic [7:0] output cas_n_gd,    ; 
  logic [7:0] output ras_n_gd,    ; 
  logic [7:0] output cs_n_gd      ;