Modelsim linter always gives 0 errors/warnings returned

[MasterJubei]

I have tried with modelsim student 10.4 and the intel 20.1 version. I am on Windows 10 x64. No matter what I do, in the output of the extension I always get:

[Info] Symbols Requested: file:///e%3A/Documents/verilog/work/test.sv c:\ctags\ctags.exe -f - --fields=+K --sort=no --excmd=n "e:\Documents\verilog\work\test.sv" [Info] 0 errors/warnings returned [Info] 5 top-level symbols returned

However when I try to compile inside of modelsim it throws errors as expected.

[danlomeli]

I'm having the same issue in Ubuntu console versus the loggin output

vlog -lint axi_scheduler_v1_0.sim/axi_scheduler_tb.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
Start time: 16:57:12 on May 10,2020
vlog -lint axi_scheduler_v1_0.sim/axi_scheduler_tb.sv 
-- Compiling module arbiter_tb
** Error: (vlog-13069) axi_scheduler_v1_0.sim/axi_scheduler_tb.sv(27): near "logic": syntax error, unexpected "SystemVerilog keyword 'logic'", expecting ';' or ','.
** Error: (vlog-13069) axi_scheduler_v1_0.sim/axi_scheduler_tb.sv(39): near "logic": syntax error, unexpected "SystemVerilog keyword 'logic'", expecting ';' or ','.
End time: 16:57:12 on May 10,2020, Elapsed time: 0:00:00
Errors: 2, Warnings: 0

verilog.linting.linter: "modelsim"

[Info] Symbols Requested: file:///home/daniel/playground/axi_scheduler/axi_scheduler_v1_0.sim/axi_scheduler_tb.sv
> /usr/local/bin/ctags -f - --fields=+K --sort=no --excmd=n "/home/daniel/playground/axi_scheduler/axi_scheduler_v1_0.sim/axi_scheduler_tb.sv"
[Info] 1 top-level symbols returned
[Info] modelsim lint requested
[Info] 0 errors/warnings returned

verilog.linting.linter: "verilator" works fine

[Info] Symbols Requested: file:///home/daniel/playground/axi_scheduler/axi_scheduler_v1_0.sim/axi_scheduler_tb.sv
> ctags -f - --fields=+K --sort=no --excmd=n "/home/daniel/playground/axi_scheduler/axi_scheduler_v1_0.sim/axi_scheduler_tb.sv"
[Info] 1 top-level symbols returned
[Info] verilator lint requested
> verilator -sv --lint-only -I/home/daniel/playground/axi_scheduler/axi_scheduler_v1_0.sim -sv --error-limit 1000 --lint-only -Werror-WIDTH -Werror-UNUSED -Wwarn-WIDTH -Wwarn-UNUSED  "/home/daniel/playground/axi_scheduler/axi_scheduler_v1_0.sim/axi_scheduler_tb.sv"
[Info] 2 errors/warnings returned

[CaiB]

Has anyone found a solution for this issue? I'm seeing the same thing.

[danlomeli]

No, I just went back to v1.0.3

[CaiB]

Thank you. I can confirm downgrading the extension to 1.0.3 immediately fixed the issue.

[CaiB]

Is there any plan to fix whatever is causing this issue?

Currently, linting breaks every time the extension gets updated until I downgrade to 1.0.3. Furthermore, if ModelSim has not been run (creating a work directory), linting also does not work. In both cases I just get no errors at all.

[MahmoudKMaarouf]

I have the same issue. I can have no path/an incorrect path for my modelsim linter and it will still report 0 errors and warnings.

This user here does not have this issue however: https://www.youtube.com/watch?v=-DTGf3Z6v_o&ab_channel=RichBaird

So I am a bit puzzled by this situation.

[danlomeli]

I was able to work around this. I had some time a few weeks ago to dig into the extension source and found the code that creates a local work dir is no longer able to do so. I created static work dir using vlib and pointed to it like this

vlib /home//work code settings.json ... "verilog.linting.modelsim.work": "/home//work" ...

[MahmoudKMaarouf]

Thanks danlomeli for your help But unfortunately, my situation still remains. I have put a work folder in my home directory /usr2/mmaarouf/work yet the issue persists

With other simulators, I can view the command in the extension output window. Then I can copy and paste that command and try it out on my linux terminal. But for modelsim, it does not show this command.

My path is pointing to Vlog and my work directory is shown as above. No sure what I am missing. Slang and icarus verilog works for me however.

[MahmoudKMaarouf]

I was able to correct this issue by correcting my Modelsim path. I had faced trouble navigating through modelsim wrappers, symbolic links, etc that would either provide errors or had renamed versions of official Modelsim commands. Thank you @danlomeli for affirming a solution was possible for this bug.

[jonpovey]

Thanks @danlomeli that fixed modelsim linting for me. For the dev - it would be great if an error was reported in the Verilog module output for cases like this, rather than just 0 errors/warnings returned