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mshr-h / vscode-verilog-hdl-support

HDL support for VS Code
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[BUG] keyword "endcase" did not match "case" when highlighting #123

Open idlesilver opened 3 years ago

idlesilver commented 3 years ago

Describe the bug The keyword "case" and "endcase" do not match with each other in highlighting brackets. (Only the "case", other keywords like module, bracket, begin/end can be highlighted normally)

Environment (please complete the following information):

Steps to reproduce Steps to reproduce the behavior: copy code

case(keycode)
    8'h1A : begin
                Ball_X_Motion_in = 0;
                Ball_Y_Motion_in = ~(Ball_Y_Step) + 1'b1;
    end
    8'h16 : begin
                Ball_X_Motion_in = 0;
                Ball_Y_Motion_in = Ball_Y_Step;
    end
    8'h04 : begin
                Ball_X_Motion_in = ~(Ball_X_Step) + 1'b1; 
                Ball_Y_Motion_in = 0;
    end
    8'h07 : begin
                Ball_X_Motion_in = Ball_X_Step;
                Ball_Y_Motion_in = 0;
    end
endcase

See error image

Expected behavior Seen "case" and "endcase" as an pair of brackets when highlighting.

Actual behavior "case" can be seen as bracket, but not "endcase"

mshr-h commented 3 years ago

Cannot reproduce the bug. It's correctly working on my PC.

Capture

idlesilver commented 3 years ago

This bug only appears when using the HIGHTLIGHT EXTENSION: Bracket Pair Colorizer 2 This extension allows matching brackets to be identified with colours. All other keywords matches each other except "case/endcase".

PanTongLin commented 3 years ago

This is because "endcase" is common end bracket for "case", "casez", and "casex" in Verilog and Systemverilog. Since "cases" and "cases" are rarely used, you can just remove them in "{EXTENSION_ROOT}/MSHR-H.VERILOGHDL-x.x.x/verilog.configuration.json" to fix this problem.

reference