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mshr-h / vscode-verilog-hdl-support

HDL support for VS Code
MIT License
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use uctag parameter field option for module instantiation (#102) #457

Closed hirooih closed 8 months ago

hirooih commented 9 months ago

NOTE: This pull request is not tested, because I don't have environment to test VS code extension.

By adding --fields-SystemVerilog=+{parameter} option uctag, it emits the 6th field, parameter:.

When parameter: is emitted, this fix override type as parameter.

In the following example parameter: are added on P1 and P2. This fix uses them.

$ cat with_parameter_port_list.sv 
module with_parameter_port_list #(
        P1,
        localparam L2 = P1+1,
        parameter P2)
        ( /*port list...*/ );
        parameter  L3 = "synonym for the localparam";
        localparam L4 = "localparam";
        // ...
endmodule

$ ctags -o - --fields=+K --sort=no --excmd=n with_parameter_port_list.sv 
with_parameter_port_list        with_parameter_port_list.sv     1;"     module
P1      with_parameter_port_list.sv     2;"     constant        module:with_parameter_port_list
L2      with_parameter_port_list.sv     3;"     constant        module:with_parameter_port_list
P2      with_parameter_port_list.sv     4;"     constant        module:with_parameter_port_list
L3      with_parameter_port_list.sv     6;"     constant        module:with_parameter_port_list
L4      with_parameter_port_list.sv     7;"     constant        module:with_parameter_port_list
$ ctags -o - --fields=+K --sort=no --excmd=n --fields-SystemVerilog=+{parameter} with_parameter_port_list.sv 
with_parameter_port_list        with_parameter_port_list.sv     1;"     module
P1      with_parameter_port_list.sv     2;"     constant        module:with_parameter_port_list parameter:
L2      with_parameter_port_list.sv     3;"     constant        module:with_parameter_port_list
P2      with_parameter_port_list.sv     4;"     constant        module:with_parameter_port_list parameter:
L3      with_parameter_port_list.sv     6;"     constant        module:with_parameter_port_list
L4      with_parameter_port_list.sv     7;"     constant        module:with_parameter_port_list
$
hirooih commented 8 months ago

@mshr-h

You are welcome.

BTW does the Instantiate Module work command on your environment? I've updated this extension. But it does not insert anything.

Here is my log.

2024-01-15 23:27:08.550 [info] mshr-h.veriloghdl is now active.
2024-01-15 23:27:08.550 [info] [ExtensionManager] previousVersion: "1.13.1", currentVersion: "1.13.1"
2024-01-15 23:27:08.550 [info] [CtagsManager] ctags manager configure
2024-01-15 23:27:08.550 [info] [LintManager] Using linter: verilator
2024-01-15 23:27:08.550 [info] [LintManager] [VerilatorLinter] [verilator] Execute
2024-01-15 23:27:08.550 [info] [LintManager] [VerilatorLinter] [verilator]   command: verilator -sv --lint-only -I"/home/hiroo/Work/GitHub/sandbox/verilog"  "/home/hiroo/Work/GitHub/sandbox/verilog/with_parameter_port_list.sv"
2024-01-15 23:27:08.550 [info] [LintManager] [VerilatorLinter] [verilator]   cwd    : /home/hiroo/Work/GitHub/sandbox
2024-01-15 23:27:08.550 [info] mshr-h.veriloghdl activation finished.
2024-01-15 23:27:08.550 [info] [LintManager] [VerilatorLinter] [verilator] 0 errors/warnings returned
2024-01-15 23:27:18.175 [info] [VerilogDocumentSymbolProvider] [VerilogSymbol] Symbols Requested: file:///home/hiroo/Work/GitHub/sandbox/verilog/with_parameter_port_list.sv
2024-01-15 23:27:18.176 [info] [CtagsManager] [Ctags] indexing...
2024-01-15 23:27:18.176 [info] [CtagsManager] [Ctags] executing ctags
2024-01-15 23:27:30.650 [info] Executing ctags for module instantiation
2024-01-15 23:27:30.650 [info] executing ctags