Closed toTheSky closed 2 weeks ago
This is fixed on https://github.com/AndrewNolte/vscode-system-verilog. It'll also fill in the instantiation as you type 'Module #(
, and it support interfaces
This is fixed on https://github.com/AndrewNolte/vscode-system-verilog. It'll also fill in the instantiation as you type
'Module #(
, and it support interfaces
Thanks. Can it be merged with the main repo?
This is fixed on https://github.com/AndrewNolte/vscode-system-verilog. It'll also fill in the instantiation as you type
'Module #(
, and it support interfacesThanks. Can it be merged with the main repo?
I forked off quite a bit to move faster with improvements, it's on the marketplace https://marketplace.visualstudio.com/items?itemName=AndrewNolte.vscode-system-verilog
Hi, I am quite sure that this problem is caused by #102 between v1.13.0 and v1.13.1. The latest version without such problem is v1.13.0. This commit should probably be reverted?
@toTheSky @RickyTino Can you test out the fix in #496? Thanks
@Raamakrishnan
Thank you for your fix.
Now I see my fixes of #457 was correct, but I had to fix one more line.
Describe the bug Module instantiation instantiates ports but not parameters.
Environment (please complete the following information):
Steps to reproduce Steps to reproduce the behavior:
Log I don't know where the log is located.
Expected behavior Parameters should be instantiated too.
Actual behavior Only ports are instantiated.
Additional context I tried to add additional arguments to ctags path (
ctags.exe --fields-Verilog=+{parameter}
) but it does't help.