Closed riuandg5 closed 3 weeks ago
I guess that your configuration uses the formatter from veribleVerilogLs. verible-verilog-ls also has the --indentation_spaces=4 setting. But I didn't find a way to pass arguments when starting the ls. When setting
verilog.languageServer.veribleVerilogLs.path": ".vscode/verible-verilog-ls --indentation_spaces=4
an error appears:
[Error - 11:36:05 AM] veribleVerilogLs language server client: couldn't create connection to server. Launching server using command .vscode/verible-verilog-ls --indentation_spaces=4 failed. Error: spawn .vscode/verible-verilog-ls --indentation_spaces=4 ENOENT
What @hi0t said is right. There are actually two same-name formatters. One is provided by the language server and another is provided by the formatter. If you manually select the formatter provided one, it works well. WHILE as their names are the same, VSCode cannot remember which formatter you want to use. I have two ideas to solve this: one is remove the ls provided formatter. Or else we can just rename it.
Edit: Seems no convenient way to either rename or disable the ls-provided one. :(
Describe the bug I changed the default indentation width from 2 to 4 by providing arguments but verilog code is still using 2 as indentation width after formatting.
Environment (please complete the following information):
Steps to reproduce
Code after formatting:
Log I don't know how to get the logs for the above format operation.
Expected behavior Verilog code should be formatted to use indentation width of 4.
Actual behavior Verilog code is being formatted with indentation width of 2.
Additional context When directly using the verible-verilog-format on command line with --indentation_spaces=4 as argument, it is working as expected.