Open NekoCWD opened 3 months ago
Copying some text from Matrix:
void __iomem *base = pll_28nm->phy->pll_base;
and error accured when any read called. example:
dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG)
dsi pll reg should be coming from here https://github.com/torvalds/linux/blob/master/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi#L1005 plus whatever offsets the driver might have
Yeah so phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", &phy->pll_size);
so that should be 0xfd922a00
and since REG_DSI_28nm_PHY_PLL_REFCLK_CFG
is 0x0
it's just that value
Can you run this in lk2nd?
$ fastboot oem readl 0xfd922a00
For me the output is
(bootloader) 0x00000001
But this also works on the Samsung:
For me also
(bootloader) 0x00000001
And for reference, with this patch I get the following print
[ 1.160583] dsi_pll_28nm_clk_recalc_rate:253 DBG base=f0e72a00
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index ceec7bb87bf1..9ed29cd224a0 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -250,6 +250,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
VERB("parent_rate=%lu", parent_rate);
/* Check to see if the ref clk doubler is enabled */
+ printk(KERN_ERR "%s:%d DBG base=%px\n", __func__, __LINE__, base);
doubler = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
ref_clk += (doubler * VCO_REF_CLK_RATE);
Were there any DTS changes necessary to get this working?
@NekoCWD Would have to share what they did, I don't have that diff/branch.
What's wrong?
When i enable mdss in dts, tablet doesn't boot
Error log
https://pastebin.com/LAVzpGL2`