FPGA clock isn't synced with the PXI

[datid]

Maybe part of the phase walking etc -

It looks like maybe we should have the Synchronize FPGA clock to PXI_Clk10 checked in the RIO device set up.

[lo-co]

Shouldn't be an issue. We don't do anything else with that clock, so we don't need to synchronize this. The phase walking is due to an incorrect number of samples, not synchronization.

[datid]

PASphase branch addresses this. Sets it to synchronized, but also uses DAQmx to ensure the 6225 card uses PXI_Clk10 as its reference clock.