Create a module (a set of classes) that is able to simulate a CPU that can execute the Instruction Set Architecture (ISA) specified in the Phase 1 document on D2L.
Requirements
The CPU must store 16 registers (r0 - r15), where r0 stores the value of the accumulator (last value generated by the ALU) and r1 always stores the value of 0. The rest of the registers are general purpose.
The CPU must store a Program Counter, an address to a location in RAM, which is used to get the next instruction that the CPU must process.
The CPU must process each instruction by: fetching the instruction from RAM, decoding the instruction, and executing the instruction based on the defined ISA.
The CPU must also utalize a DMA-Channel, which is a module that handles all I/O-operations to the Memory System.
CPU Module
Objective
Create a module (a set of classes) that is able to simulate a CPU that can execute the Instruction Set Architecture (ISA) specified in the Phase 1 document on D2L.
Requirements