w5500 very good, few timeouts

jschoch commented 5 months ago

here's my compile log output, hoping there is something in here regarding timing that makes for more stable w5500. What ever it did it seems much much more stable than previous builds

rm -rf rio.fs rio.json rio_pnr.json rio.tcl abc.history impl yosys.log
yosys -q -l yosys.log -p 'synth_gowin -noalu -nowidelut -top rio -json rio.json' w5500.v quadencoderz.v blink.v stepdir.v debouncer.v toggle.v rio.v
nextpnr-gowin --seed 0 --json rio.json --write rio_pnr.json --freq 27.0 --enable-globals --enable-auto-longwires --device GW1NR-LV9QN88PC6/I5 --cst pins.cst
Info: Series:GW1N-9 Device:GW1NR-9 Package:QFN88P Speed:C6/I5

Info: Packing constants..
Info: Packing Shadow RAM..
Info: Packing GSR..
Info: No GSR in the chip base
Info: Packing IOs..
Info: Packing diff IOs..
Info: Packing IO logic..
Info: Packing wide LUTs..
Info: Packing LUT5s..
Info: Packing LUT6s..
Info: Packing LUT7s..
Info: Packing LUT8s..
Info: Packing ALUs..
Info: Packing LUT-FFs..
Info: Packing non-LUT FFs..
Info: Packing PLLs..
Info: Checksum: 0xb65def86

Info: Device utilisation:
Info:                    VCC:     1/    1   100%
Info:                  SLICE:  1882/ 8640    21%
Info:                    IOB:    16/  274     5%
Info:                 OSER16:     0/   38     0%
Info:                 IDES16:     0/   38     0%
Info:                IOLOGIC:     0/  296     0%
Info:              MUX2_LUT5:     0/ 4320     0%
Info:              MUX2_LUT6:     0/ 2160     0%
Info:              MUX2_LUT7:     0/ 1080     0%
Info:              MUX2_LUT8:     0/ 1056     0%
Info:                    GND:     1/    1   100%
Info:                   RAMW:     0/  270     0%
Info:                    OSC:     0/    1     0%
Info:                   rPLL:     0/    2     0%

Info: Placed 16 cells based on constraints.
Info: Creating initial analytic placement for 1884 cells, random placement wirelen = 64840.
Info:     at initial placer iter 0, wirelen = 520
Info:     at initial placer iter 1, wirelen = 550
Info:     at initial placer iter 2, wirelen = 531
Info:     at initial placer iter 3, wirelen = 569
Info: Running main analytical placer, max placement attempts per cell = 451250.
Info:     at iteration #1, type ALL: wirelen solved = 562, spread = 8661, legal = 8730; time = 0.45s
Info:     at iteration #2, type ALL: wirelen solved = 1118, spread = 7541, legal = 7743; time = 0.38s
Info:     at iteration #3, type ALL: wirelen solved = 1406, spread = 7254, legal = 7361; time = 0.32s
Info:     at iteration #4, type ALL: wirelen solved = 1776, spread = 6888, legal = 6998; time = 0.23s
Info:     at iteration #5, type ALL: wirelen solved = 2068, spread = 6793, legal = 6791; time = 0.33s
Info:     at iteration #6, type ALL: wirelen solved = 2351, spread = 6453, legal = 6454; time = 0.33s
Info:     at iteration #7, type ALL: wirelen solved = 2570, spread = 6299, legal = 6299; time = 0.29s
Info:     at iteration #8, type ALL: wirelen solved = 2775, spread = 6149, legal = 6148; time = 0.32s
Info:     at iteration #9, type ALL: wirelen solved = 3013, spread = 6179, legal = 6255; time = 0.22s
Info:     at iteration #10, type ALL: wirelen solved = 3309, spread = 6214, legal = 6275; time = 0.21s
Info:     at iteration #11, type ALL: wirelen solved = 3503, spread = 7334, legal = 7381; time = 0.28s
Info:     at iteration #12, type ALL: wirelen solved = 3885, spread = 6930, legal = 7012; time = 0.33s
Info:     at iteration #13, type ALL: wirelen solved = 3976, spread = 6636, legal = 6695; time = 0.26s
Info: HeAP Placer Time: 6.29s
Info:   of which solving equations: 4.89s
Info:   of which spreading cells: 0.45s
Info:   of which strict legalisation: 0.13s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 659, wirelen = 6148
Info:   at iteration #5: temp = 0.000000, timing cost = 522, wirelen = 5243
Info:   at iteration #10: temp = 0.000000, timing cost = 510, wirelen = 4805
Info:   at iteration #15: temp = 0.000000, timing cost = 474, wirelen = 4619
Info:   at iteration #20: temp = 0.000000, timing cost = 527, wirelen = 4468
Info:   at iteration #24: temp = 0.000000, timing cost = 449, wirelen = 4414 
Info: SA placement time 15.77s

Info: Max frequency for clock      'sysclk': 44.41 MHz (PASS at 27.00 MHz)
Info: Max frequency for clock 'w55000.mclk': 42.28 MHz (PASS at 27.00 MHz)

Info: Max delay <async>             -> posedge sysclk     : 5.20 ns
Info: Max delay <async>             -> posedge w55000.mclk: 14.80 ns
Info: Max delay posedge sysclk      -> <async>            : 16.06 ns
Info: Max delay posedge sysclk      -> posedge w55000.mclk: 2.06 ns
Info: Max delay posedge w55000.mclk -> <async>            : 33.81 ns
Info: Max delay posedge w55000.mclk -> posedge sysclk     : 23.81 ns

Info: Slack histogram:
Info:  legend: * represents 14 endpoint(s)
Info:          + represents [1,14) endpoint(s)
Info: [ 13383,  14523) |+
Info: [ 14523,  15663) |+
Info: [ 15663,  16803) |*+
Info: [ 16803,  17943) |*+
Info: [ 17943,  19083) |**+
Info: [ 19083,  20223) |*+
Info: [ 20223,  21363) |**+
Info: [ 21363,  22503) |**+
Info: [ 22503,  23643) |**+
Info: [ 23643,  24783) |**+
Info: [ 24783,  25923) |**+
Info: [ 25923,  27063) |*+
Info: [ 27063,  28203) |**+
Info: [ 28203,  29343) |**+
Info: [ 29343,  30483) |**+
Info: [ 30483,  31623) |**+
Info: [ 31623,  32763) |***+
Info: [ 32763,  33903) |***+
Info: [ 33903,  35043) |********+
Info: [ 35043,  36183) |************************************************************ 
Info: Checksum: 0xf3421833
Info: Find global nets...
Info:  Non clock source, skip w55000.mclk.
Info: Routing globals...
Info:   Route net sysclk, use clock #0.
Info:   Net sysclk is routed.

Info: Routing..
Info: Setting up routing queue.
Info: Routing 6022 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      115        884 |  115   884 |      5270|       2.55       2.55|
Info:       2000 |      365       1634 |  250   750 |      4632|       1.68       4.23|
Info:       3000 |      640       2359 |  275   725 |      4034|       1.45       5.68|
Info:       4000 |      904       3095 |  264   736 |      3386|       1.51       7.19|
Info:       5000 |     1123       3876 |  219   781 |      2682|       1.16       8.35|
Info:       6000 |     1273       4726 |  150   850 |      1871|       0.98       9.33|
Info:       7000 |     1453       5546 |  180   820 |      1112|       1.32      10.65|
Info:       8000 |     1695       6304 |  242   758 |       463|       3.03      13.68|
Info:       9000 |     2054       6945 |  359   641 |       132|       2.62      16.31|
Info:       9203 |     2104       7099 |   50   154 |         0|       0.72      17.02|
Info: Routing complete.
Info: Router1 time 17.02s
Info: Checksum: 0xd602fa08

Info: Critical path report for clock 'sysclk' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source stepdir4.jointCounter_DFF_Q_30_D_LUT3_F_LC.Q
Info:  0.4  0.9    Net stepdir4.jointCounter[1] (28,14) -> (28,15)
Info:                Sink stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_I1_LUT2_F_1_I0_LUT4_F_1_I0_LUT4_F_LC.B
Info:                Defined in:
Info:                  rio.v:152.13-160.6
Info:                  stepdir.v:13.16-13.28
Info:  1.1  2.0  Source stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_I1_LUT2_F_1_I0_LUT4_F_1_I0_LUT4_F_LC.F
Info:  0.4  2.4    Net stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_I1_LUT2_F_1_I0_LUT4_F_1_I0[0] (28,15) -> (29,15)
Info:                Sink stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_I1_LUT2_F_1_I0_LUT4_F_1_LC.A
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.0  3.4  Source stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_I1_LUT2_F_1_I0_LUT4_F_1_LC.F
Info:  0.4  3.8    Net stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_I1_LUT2_F_1_I0[0] (29,15) -> (29,14)
Info:                Sink stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_I1_LUT2_F_1_LC.A
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.0  4.9  Source stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_I1_LUT2_F_1_LC.F
Info:  0.4  5.3    Net stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_I1[2] (29,14) -> (28,14)
Info:                Sink stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_LC.C
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.8  6.1  Source stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0_LUT4_F_LC.F
Info:  0.3  6.4    Net stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_I0[0] (28,14) -> (28,14)
Info:                Sink stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_LC.A
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.0  7.4  Source stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0_LUT4_F_3_LC.F
Info:  0.9  8.3    Net stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_I0[1] (28,14) -> (27,13)
Info:                Sink stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_LC.B
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.1  9.4  Source stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0_LUT4_F_1_LC.F
Info:  0.0  9.4    Net stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_I0[0] (27,13) -> (27,13)
Info:                Sink stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_LC.A
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.0 10.5  Source stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0_LUT2_F_LC.F
Info:  0.4 10.9    Net stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_I0[1] (27,13) -> (26,13)
Info:                Sink stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_LC.B
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.1 12.0  Source stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_1_LC.F
Info:  0.8 12.8    Net stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_I0[1] (26,13) -> (24,13)
Info:                Sink stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_LC.B
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.1 13.9  Source stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0_LUT4_F_1_LC.F
Info:  0.0 13.9    Net stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_I0[1] (24,13) -> (24,13)
Info:                Sink stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_LC.B
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.1 15.0  Source stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F_LUT4_F_LC.F
Info:  0.5 15.5    Net stepdir4.velocityAbs_DFF_Q_3_D_LUT3_F_I1_LUT4_I3_F[2] (24,13) -> (26,13)
Info:                Sink stepdir4.en_LUT4_I3_LC.C
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.8 16.3  Source stepdir4.en_LUT4_I3_LC.F
Info:  1.4 17.6    Net stepdir4.en_LUT4_I3_F[0] (26,13) -> (29,14)
Info:                Sink stepdir4.jointCounter_DFF_Q_28_D_LUT2_F_LC.A
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.0 17.6  Setup stepdir4.jointCounter_DFF_Q_28_D_LUT2_F_LC.A
Info: 11.7 ns logic, 5.9 ns routing

Info: Critical path report for clock 'w55000.mclk' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source w55000.eth_iface.spi_clock_count_DFFRE_Q_8_D_LUT3_F_LC.Q
Info:  2.9  3.3    Net w55000.eth_iface.spi_clock_count[1] (14,14) -> (9,8)
Info:                Sink w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_I3_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  4.0  Source w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_I3_LUT4_F_LC.F
Info:  0.3  4.3    Net w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_I3[3] (9,8) -> (9,8)
Info:                Sink w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  4.9  Source w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I0_LUT4_F_LC.F
Info:  0.8  5.7    Net w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I0[2] (9,8) -> (9,10)
Info:                Sink w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_LC.C
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.8  6.5  Source w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_LC.F
Info:  2.9  9.4    Net w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0[1] (9,10) -> (11,19)
Info:                Sink w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT3_I0_LC.B
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.1 10.5  Source w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT3_I0_LC.F
Info:  0.0 10.5    Net w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT3_I0_F[2] (11,19) -> (11,19)
Info:                Sink w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT3_I0_F_LUT4_I0_LC.C
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.8 11.3  Source w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT4_F_I0_LUT3_I0_F_LUT4_I0_LC.F
Info:  0.9 12.2    Net w55000.eth_iface.spi_clock_count_DFFRE_Q_7_D_LUT3_F_I1_LUT4_I3_F_LUT4_I0_F_LUT4_F_1_I0[0] (11,19) -> (11,17)
Info:                Sink w55000.eth_iface.spi_clock_count_DFFRE_Q_7_D_LUT3_F_I1_LUT4_I3_F_LUT4_I0_F_LUT4_F_1_LC.A
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.0 13.3  Source w55000.eth_iface.spi_clock_count_DFFRE_Q_7_D_LUT3_F_I1_LUT4_I3_F_LUT4_I0_F_LUT4_F_1_LC.F
Info:  0.3 13.6    Net w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I1[2] (11,17) -> (11,17)
Info:                Sink w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I1_LUT4_F_I0_LUT4_F_1_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 14.2  Source w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I1_LUT4_F_I0_LUT4_F_1_LC.F
Info:  0.3 14.5    Net w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I1_LUT4_F_I0[3] (11,17) -> (11,17)
Info:                Sink w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 15.2  Source w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I1_LUT4_F_LC.F
Info:  0.0 15.2    Net w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_I1[1] (11,17) -> (11,17)
Info:                Sink w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_LC.B
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.1 16.3  Source w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0_LUT4_F_1_LC.F
Info:  0.4 16.7    Net w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_I0[3] (11,17) -> (12,17)
Info:                Sink w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 17.3  Source w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0_LUT4_F_LC.F
Info:  0.3 17.6    Net w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_I0[0] (12,17) -> (12,17)
Info:                Sink w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_LC.A
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.0 17.6  Setup w55000.eth_iface.mosi_DFFE_Q_D_LUT4_F_LC.A
Info: 8.5 ns logic, 9.2 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge sysclk':
Info: curr total
Info:  0.0  0.0  Source quadencoderz1.z_IBUF_O$iob.O
Info:  2.9  2.9    Net quadencoderz1.z (12,28) -> (8,20)
Info:                Sink quadencoderz1.quadZ_delayed_DFF_Q_2_DFFLC.A
Info:                Defined in:
Info:                  rio.v:128.7-136.6
Info:                  quadencoderz.v:11.16-11.17
Info:  0.0  2.9  Setup quadencoderz1.quadZ_delayed_DFF_Q_2_DFFLC.A
Info: 0.0 ns logic, 2.9 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge w55000.mclk':
Info: curr total
Info:  0.0  0.0  Source w55000.eth_iface.miso_IBUF_O$iob.O
Info:  8.6  8.6    Net w55000.miso (37,0) -> (14,13)
Info:                Sink w55000.eth_iface.data_read_DFFE_Q_7_DFFLC.A
Info:                Defined in:
Info:                  rio.v:113.7-123.6
Info:                  w5500.v:15.16-15.20
Info:  0.0  8.6  Setup w55000.eth_iface.data_read_DFFE_Q_7_DFFLC.A
Info: 0.0 ns logic, 8.6 ns routing

Info: Critical path report for cross-domain path 'posedge sysclk' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source stepdir5.step_LUT1_I0_LC.Q
Info:  9.1  9.6    Net stepdir5.en_LUT4_I3_F_LUT3_I0_F[1] (8,22) -> (40,28)
Info:                Sink PINOUT_STEPDIR5_STEP_OBUF_O$iob.I
Info:                Defined in:
Info:                  rio.v:163.13-171.6
Info:                  stepdir.v:9.20-9.24
Info: 0.5 ns logic, 9.1 ns routing

Info: Critical path report for cross-domain path 'posedge sysclk' -> 'posedge w55000.mclk':
Info: curr total
Info:  0.5  0.5  Source stepdir5.positionMem_DFFE_Q_7_D_LUT4_F_LC.Q
Info:  1.3  1.7    Net VARIN32_STEPDIR5_POSITION[24] (6,14) -> (8,13)
Info:                Sink w55000.data_to_ethernet_DFFE_Q_94_DFFLC.A
Info:                Defined in:
Info:                  rio.v:113.7-123.6
Info:                  w5500.v:18.34-18.41
Info:  0.0  1.7  Setup w55000.data_to_ethernet_DFFE_Q_94_DFFLC.A
Info: 0.5 ns logic, 1.3 ns routing

Info: Critical path report for cross-domain path 'posedge w55000.mclk' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source w55000.eth_iface.data_output_DFFE_Q_38_DFFLC.Q
Info:  0.3  0.8    Net VAROUT32_STEPDIR5_VELOCITY[1] (2,24) -> (2,24)
Info:                Sink stepdir5.velocityAbs_DFF_Q_27_D_LUT3_F_I1_LUT4_F_LC.B
Info:                Defined in:
Info:                  rio.v:113.7-123.6
Info:                  w5500.v:19.35-19.42
Info:  1.1  1.9  Source stepdir5.velocityAbs_DFF_Q_27_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.9  2.8    Net stepdir5.velocityAbs_DFF_Q_27_D_LUT3_F_I1[3] (2,24) -> (2,21)
Info:                Sink stepdir5.velocityAbs_DFF_Q_24_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  3.4  Source stepdir5.velocityAbs_DFF_Q_24_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.4  3.8    Net stepdir5.velocityAbs_DFF_Q_24_D_LUT3_F_I1[3] (2,21) -> (2,20)
Info:                Sink stepdir5.velocityAbs_DFF_Q_21_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  4.4  Source stepdir5.velocityAbs_DFF_Q_21_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.4  4.8    Net stepdir5.velocityAbs_DFF_Q_21_D_LUT3_F_I1[3] (2,20) -> (2,19)
Info:                Sink stepdir5.velocityAbs_DFF_Q_18_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  5.5  Source stepdir5.velocityAbs_DFF_Q_18_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.8  6.3    Net stepdir5.velocityAbs_DFF_Q_18_D_LUT3_F_I1[3] (2,19) -> (2,17)
Info:                Sink stepdir5.velocityAbs_DFF_Q_15_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  6.9  Source stepdir5.velocityAbs_DFF_Q_15_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.8  7.7    Net stepdir5.velocityAbs_DFF_Q_15_D_LUT3_F_I1[3] (2,17) -> (2,15)
Info:                Sink stepdir5.velocityAbs_DFF_Q_12_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  8.3  Source stepdir5.velocityAbs_DFF_Q_12_D_LUT3_F_I1_LUT4_F_LC.F
Info:  1.2  9.5    Net stepdir5.velocityAbs_DFF_Q_12_D_LUT3_F_I1[3] (2,15) -> (4,14)
Info:                Sink stepdir5.velocityAbs_DFF_Q_9_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 10.2  Source stepdir5.velocityAbs_DFF_Q_9_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.3 10.5    Net stepdir5.velocityAbs_DFF_Q_9_D_LUT3_F_I1[3] (4,14) -> (4,14)
Info:                Sink stepdir5.velocityAbs_DFF_Q_6_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 11.1  Source stepdir5.velocityAbs_DFF_Q_6_D_LUT3_F_I1_LUT4_F_LC.F
Info:  1.2 12.3    Net stepdir5.velocityAbs_DFF_Q_6_D_LUT3_F_I1[3] (4,14) -> (6,15)
Info:                Sink stepdir5.en_LUT4_I3_F_LUT4_F_I3_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 13.0  Source stepdir5.en_LUT4_I3_F_LUT4_F_I3_LUT4_F_LC.F
Info:  0.5 13.4    Net stepdir5.en_LUT4_I3_F_LUT4_F_I3[3] (6,15) -> (6,17)
Info:                Sink stepdir5.en_LUT4_I3_F_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 14.1  Source stepdir5.en_LUT4_I3_F_LUT4_F_LC.F
Info:  0.4 14.5    Net stepdir5.en_LUT4_I3_F[0] (6,17) -> (5,17)
Info:                Sink stepdir5.dir_LUT2_F_LC.A
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.0 15.5  Source stepdir5.dir_LUT2_F_LC.F
Info:  8.6 24.1    Net stepdir5.dir (5,17) -> (28,28)
Info:                Sink PINOUT_STEPDIR5_DIR_OBUF_O$iob.I
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info: 8.2 ns logic, 15.9 ns routing

Info: Critical path report for cross-domain path 'posedge w55000.mclk' -> 'posedge sysclk':
Info: curr total
Info:  0.5  0.5  Source w55000.eth_iface.data_output_DFFE_Q_38_DFFLC.Q
Info:  0.3  0.8    Net VAROUT32_STEPDIR5_VELOCITY[1] (2,24) -> (2,24)
Info:                Sink stepdir5.velocityAbs_DFF_Q_27_D_LUT3_F_I1_LUT4_F_LC.B
Info:                Defined in:
Info:                  rio.v:113.7-123.6
Info:                  w5500.v:19.35-19.42
Info:  1.1  1.9  Source stepdir5.velocityAbs_DFF_Q_27_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.9  2.8    Net stepdir5.velocityAbs_DFF_Q_27_D_LUT3_F_I1[3] (2,24) -> (2,21)
Info:                Sink stepdir5.velocityAbs_DFF_Q_24_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  3.4  Source stepdir5.velocityAbs_DFF_Q_24_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.4  3.8    Net stepdir5.velocityAbs_DFF_Q_24_D_LUT3_F_I1[3] (2,21) -> (2,20)
Info:                Sink stepdir5.velocityAbs_DFF_Q_21_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  4.4  Source stepdir5.velocityAbs_DFF_Q_21_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.4  4.8    Net stepdir5.velocityAbs_DFF_Q_21_D_LUT3_F_I1[3] (2,20) -> (2,19)
Info:                Sink stepdir5.velocityAbs_DFF_Q_18_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  5.5  Source stepdir5.velocityAbs_DFF_Q_18_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.8  6.3    Net stepdir5.velocityAbs_DFF_Q_18_D_LUT3_F_I1[3] (2,19) -> (2,17)
Info:                Sink stepdir5.velocityAbs_DFF_Q_15_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  6.9  Source stepdir5.velocityAbs_DFF_Q_15_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.8  7.7    Net stepdir5.velocityAbs_DFF_Q_15_D_LUT3_F_I1[3] (2,17) -> (2,15)
Info:                Sink stepdir5.velocityAbs_DFF_Q_12_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6  8.3  Source stepdir5.velocityAbs_DFF_Q_12_D_LUT3_F_I1_LUT4_F_LC.F
Info:  1.2  9.5    Net stepdir5.velocityAbs_DFF_Q_12_D_LUT3_F_I1[3] (2,15) -> (4,14)
Info:                Sink stepdir5.velocityAbs_DFF_Q_9_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 10.2  Source stepdir5.velocityAbs_DFF_Q_9_D_LUT3_F_I1_LUT4_F_LC.F
Info:  0.3 10.5    Net stepdir5.velocityAbs_DFF_Q_9_D_LUT3_F_I1[3] (4,14) -> (4,14)
Info:                Sink stepdir5.velocityAbs_DFF_Q_6_D_LUT3_F_I1_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 11.1  Source stepdir5.velocityAbs_DFF_Q_6_D_LUT3_F_I1_LUT4_F_LC.F
Info:  1.2 12.3    Net stepdir5.velocityAbs_DFF_Q_6_D_LUT3_F_I1[3] (4,14) -> (6,15)
Info:                Sink stepdir5.en_LUT4_I3_F_LUT4_F_I3_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 13.0  Source stepdir5.en_LUT4_I3_F_LUT4_F_I3_LUT4_F_LC.F
Info:  0.5 13.4    Net stepdir5.en_LUT4_I3_F_LUT4_F_I3[3] (6,15) -> (6,17)
Info:                Sink stepdir5.en_LUT4_I3_F_LUT4_F_LC.D
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.6 14.1  Source stepdir5.en_LUT4_I3_F_LUT4_F_LC.F
Info:  0.4 14.5    Net stepdir5.en_LUT4_I3_F[0] (6,17) -> (5,17)
Info:                Sink stepdir5.dir_LUT2_F_LC.A
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  1.0 15.5  Source stepdir5.dir_LUT2_F_LC.F
Info:  2.7 18.2    Net stepdir5.dir (5,17) -> (9,22)
Info:                Sink stepdir5.positionMem_DFFE_Q_30_D_LUT3_F_LC.A
Info:                Defined in:
Info:                  /usr/bin/../share/yosys/gowin/cells_map.v:130.20-130.21
Info:  0.0 18.2  Setup stepdir5.positionMem_DFFE_Q_30_D_LUT3_F_LC.A
Info: 8.2 ns logic, 10.0 ns routing

Info: Max frequency for clock      'sysclk': 56.67 MHz (PASS at 27.00 MHz)
Info: Max frequency for clock 'w55000.mclk': 56.77 MHz (PASS at 27.00 MHz)

Info: Max delay <async>             -> posedge sysclk     : 2.87 ns
Info: Max delay <async>             -> posedge w55000.mclk: 8.63 ns
Info: Max delay posedge sysclk      -> <async>            : 9.56 ns
Info: Max delay posedge sysclk      -> posedge w55000.mclk: 1.74 ns
Info: Max delay posedge w55000.mclk -> <async>            : 24.07 ns
Info: Max delay posedge w55000.mclk -> posedge sysclk     : 18.24 ns

Info: Slack histogram:
Info:  legend: * represents 12 endpoint(s)
Info:          + represents [1,12) endpoint(s)
Info: [ 19390,  20250) |*+
Info: [ 20250,  21110) |***+
Info: [ 21110,  21970) |**+
Info: [ 21970,  22830) |*+
Info: [ 22830,  23690) |**+
Info: [ 23690,  24550) |**+
Info: [ 24550,  25410) |**+
Info: [ 25410,  26270) |*+
Info: [ 26270,  27130) |**+
Info: [ 27130,  27990) |**+
Info: [ 27990,  28850) |**+
Info: [ 28850,  29710) |*+
Info: [ 29710,  30570) |***+
Info: [ 30570,  31430) |*+
Info: [ 31430,  32290) |**+
Info: [ 32290,  33150) |**+
Info: [ 33150,  34010) |**+
Info: [ 34010,  34870) |****+
Info: [ 34870,  35730) |*************+
Info: [ 35730,  36590) |************************************************************ 

Info: Program finished normally.
gowin_pack -d GW1N-9C -o rio.fs rio_pnr.json
cp -v hash_new.txt hash_compiled.txt
'hash_new.txt' -> 'hash_compiled.txt'

jschoch commented 5 months ago

this seems to have been a fluke... I get all sorts of errors when I moved the 9k out to the garage.

when i run wireshark it shows that there is an ARP and then immediately following the response the data segment of the following udp packet is duplicated and the length is doubled. not sure how this impacts the test-gui but it would be good to know if the socket timeout on the python side coincides with this problem. It is also odd that there are ICMP packets in there randomly. there is some setting for ICMP blocking or no-blocking that maybe is to blame.

I don't know enough verilog (or in general) to understand the gateware or how it deals with the flags Sn_IMR / Sn_IR but maybe it is ignoring the SEND_OK flag or something?

multigcs commented 5 months ago

i have to check this, but please can you try to build the gateware with the gowin toolchain, i think nextpnr/ypsys have some issues

jschoch commented 5 months ago

I attempted to get the code up and running in the gowin IDE last night. I had it running in GAO but I couldn't get it to do anything other than waffle between state 1 (idle) and 2 (sending command).

Can you clarify how it works? It seems that it waits for a packet, then immediately responds with a status update. There doesn't appear to be any initialization or setup of a "connection", it just seems to respond.

multigcs commented 5 months ago

I don't quite understand your question, if the IDE is in the PATH, you can move the gateway directory start the compile with :

#riocore/Output/Tangoboard/Gateware# make clean gowin_build

and flash with:

#riocore/Output/Tangoboard/Gateware# make gowin_load

rm -rf rio.fs rio.json rio_pnr.json rio.tcl abc.history impl yosys.log
gw_sh rio.tcl
*** GOWIN Tcl Command Line Console  *** 
current device: GW1NR-9C  GW1NR-LV9QN88PC6/I5
add new file: "pwmout.v"
add new file: "stepdir.v"
add new file: "modbus.v"
add new file: "uart_baud.v"
add new file: "uart_rx.v"
add new file: "uart_tx.v"
add new file: "w5500.v"
add new file: "debouncer.v"
add new file: "toggle.v"
add new file: "rio.v"
add new file: "pins.cst"
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/pwmout.v'
Analyzing Verilog file '/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/stepdir.v'
Analyzing Verilog file '/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/modbus.v'
Analyzing Verilog file '/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/uart_baud.v'
Analyzing Verilog file '/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/uart_rx.v'
Analyzing Verilog file '/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/uart_tx.v'
Analyzing Verilog file '/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/w5500.v'
Analyzing Verilog file '/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/debouncer.v'
Analyzing Verilog file '/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/toggle.v'
Analyzing Verilog file '/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/rio.v'
Compiling module 'rio'("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/rio.v":49)
WARN  (EX3780) : Using initial value of 'ESTOP' since it is never assigned("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/rio.v":88)
Compiling module 'pwmout(DIVIDER=2700)'("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/pwmout.v":2)
Compiling module 'pwmout(DIVIDER=18000)'("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/pwmout.v":2)
Compiling module 'stepdir'("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/stepdir.v":2)
WARN  (EX3791) : Expression size 9 truncated to fit in target size 8("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/rio.v":370)
Compiling module 'modbus(RX_BUFFERSIZE=128,TX_BUFFERSIZE=128,ClkFrequency=27000000)'("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/modbus.v":2)
Compiling module 'uart_rx(ClkFrequency=27000000,Baud=9600)'("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/uart_rx.v":4)
Compiling module 'uart_baud(ClkFrequency=27000000,Baud=9600,Oversampling=8)'("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/uart_baud.v":4)
WARN  (EX3791) : Expression size 9 truncated to fit in target size 8("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/modbus.v":53)
WARN  (EX3791) : Expression size 9 truncated to fit in target size 8("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/modbus.v":60)
Compiling module 'uart_tx(ClkFrequency=27000000,Baud=9600)'("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/uart_tx.v":4)
Compiling module 'uart_baud(ClkFrequency=27000000,Baud=9600)'("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/uart_baud.v":4)
WARN  (EX3791) : Expression size 9 truncated to fit in target size 8("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/modbus.v":86)
WARN  (EX3791) : Expression size 9 truncated to fit in target size 8("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/modbus.v":95)
WARN  (EX3791) : Expression size 32 truncated to fit in target size 8("/data2/src/ICE40-2023/serial-tx/riocore/Output/Tangoboard/Gateware/modbus.v":99)
...

jschoch commented 5 months ago

I'm just wondering how the w5500.v works, that is what my question above was about.

but you got me thinking about the build env and my first attempts were built in WSL, and flashed with the gowin programmer.

In my x64 debian bookworm machine (the one I have been testing with) just took a look at the version of yosys and it is 0.23. going to see how updating that changes things.

jschoch commented 5 months ago

using the gowin_build the stability is night and day better. Wireshark shows none of the double data length packets with the repeated data segment (34 len, with the 17 repeated twice in the data section of the UDP packet). I haven't tried the new yosys build yet, it took like 3 hours to build.

I'd love to try to figure out what the issue is but I need a better understanding of how the module works and how to tests it.

multigcs commented 5 months ago

initialization:

end else if (state == STATE_INITIALIZING) begin
..

check if socket is open:

end else if (state == STATE_INITIALIZING && waiting_for_socket == 1'b1) begin
...

wait for new package:

    end else if (state == STATE_IDLE) begin
        if (rx_timer == 4'd10) begin
            // check for new data
            if (is_check_rx == 1) begin
                // check poll result (data len > 0)
                if (data_read[7:0] > 8'b0) begin
                    state <= STATE_RX_START;
                end
            end else begin
                // poll command (have you rx data ?)
            end

check size of received data:

    end else if (state == STATE_RX_START) begin
        rx_buffer_read_pointer <= rx_buffer_read_pointer + data_read[7:0];
        if (rx_size == (BUFFER_SIZE_RX+HEADER_SIZE)) begin
            rx_buffer_valid <= 1;
    ...

if ok, reading receive buffer:

    end else if (state == STATE_PULLING_DATA && spi_clock_count > (rx_size+24-1)) begin
    ...

check if header is ok:

    if (rx_buffer[BUFFER_SIZE_RX-1:BUFFER_SIZE_RX-32] == MSGID) begin

get destination ip and port from the reive header:

        dst_ip <= rx_buffer[BUFFER_SIZE_RX+HEADER_SIZE-HEADER_IP_OFFSET-1:BUFFER_SIZE_RX+HEADER_SIZE-HEADER_IP_OFFSET-32];
        dst_port <= rx_buffer[BUFFER_SIZE_RX+HEADER_SIZE-HEADER_PORT_OFFSET-1:BUFFER_SIZE_RX+HEADER_SIZE-HEADER_PORT_OFFSET-16];

back in the main module: check the data_output_valid flag (means data is received / wiznet5500 module data output is valid)

always @(posedge mclk) begin
    sync <= 0;
    if (data_output_valid == 1) begin
        do_transmit <= 1;
        timeout_counter <= 0;
        pkg_timeout <= 0;
        sync <= 1;
...

do_transmit <= 1 starts the trasmission
```
...
```

jschoch commented 4 months ago

closing this, yosys doesn't work with the UDP code, you must use the gowin tools to get it to work without lots of packet errors, double packets etc.

multigcs / riocore

w5500 very good, few timeouts #2