[tricore] 64 bit registers in DVINIT instruction

Describe the bug To better compliance to other DVxx instructions, please use pair of 32-bit registers instead of one 64-bit. It also improves generated code.
I rewrote your code as follows:
@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
# DVINIT E[c], D[a], D[b] (RR)
:dvinit Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x1a0
{
    #TODO  divide sequence
    local dividend:4 = Rd0811;      # D[a]
    local divisor:4 = Rd1215;       # D[b]

    Ree2831 = dividend;
    Reo2831 = 0xFFFFFFFF * zext(dividend[31,1]);
    $(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0x80000000)));
    $(PSW_SV) = $(PSW_V) | $(PSW_SV);
    $(PSW_AV) = 0;
}
@endif

@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
# DVINIT.B E[c], D[a], D[b] (RR)
:dvinit.b Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x5a0
{
    #TODO  divide sequence
    local dividend:4 = Rd0811;      # D[a]
    local divisor:4 = Rd1215;       # D[b]
    local quotient_sign = !(dividend[31,1] == divisor[31,1]);

    Ree2831 = (dividend << 24) | (0xFFFFFF * zext(quotient_sign));
    Reo2831 = dividend s>> 8;
    $(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0xFFFFFF80)));
    $(PSW_SV) = $(PSW_V) | $(PSW_SV);
    $(PSW_AV) = 0;
}
@endif

@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
# DVINIT.BU E[c], D[a], D[b] (RR)
:dvinit.bu Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x4a0
{
    #TODO  divide sequence
    local dividend:4 = Rd0811;      # D[a]
    local divisor:4 = Rd1215;       # D[b]

    Ree2831 = dividend << 24;
    Reo2831 = dividend >> 8;
    $(PSW_V) = (divisor == 0);
    $(PSW_SV) = $(PSW_V) | $(PSW_SV);
    $(PSW_AV) = 0;
}
@endif

@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
# DVINIT.H E[c], D[a], D[b] (RR)
:dvinit.h Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x3a0
{
    #TODO  divide sequence
    local dividend:4 = Rd0811;      # D[a]
    local divisor:4 = Rd1215;       # D[b]
    local quotient_sign = !(dividend[31,1] == divisor[31,1]);

    Ree2831 = (dividend << 16) | (zext(quotient_sign) * 0xFFFF);
    Reo2831 = dividend s>> 16;
    $(PSW_V) = ((divisor == 0) || ((divisor == 0xFFFFFFFF) && (dividend == 0xFFFF8000)));
    $(PSW_SV) = $(PSW_V) | $(PSW_SV);
    $(PSW_AV) = 0;
}
@endif

@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
# DVINIT.HU E[c], D[a], D[b] (RR)
:dvinit.hu Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0x2a0
{
    #TODO  divide sequence
    local dividend:4 = Rd0811;      # D[a]
    local divisor:4 = Rd1215;       # D[b]

    Ree2831 = dividend << 16;
    Reo2831 = dividend >> 16;
    $(PSW_V) = (divisor == 0);
    $(PSW_SV) = $(PSW_V) | $(PSW_SV);
    $(PSW_AV) = 0;
}
@endif

@if defined(TRICORE_RIDER_B) || defined(TRICORE_RIDER_D) || defined(TRICORE_V2)
# DVINIT.U E[c], D[a], D[b] (RR)
:dvinit.u Ree2831/Reo2831,Rd0811,Rd1215 is PCPMode=0 & Rd0811 & Rd1215 & op0007=0x4b ; Ree2831 & Reo2831 & op1627=0xa0
{
    #TODO  divide sequence
    local dividend:4 = Rd0811;      # D[a]
    local divisor:4 = Rd1215;       # D[b]

    Ree2831 = dividend;
    Reo2831 = 0;
    $(PSW_V) = (divisor == 0);
    $(PSW_SV) = $(PSW_V) | $(PSW_SV);
    $(PSW_AV) = 0;
}
@endif
mumbel / ghidra

[tricore] 64 bit registers in DVINIT instruction #20
