Closed mvnmgrx closed 2 years ago
The PCB stackup can be expanded with additional dielectric layers, as seen below, which will not be picked up by the parser.
TODO:
Possible test case:
(stackup (layer "F.SilkS" (type "Top Silk Screen") (color "White")) (layer "F.Paste" (type "Top Solder Paste")) (layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01) (material "Epoxy") (epsilon_r 3.3) (loss_tangent 0)) (layer "F.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 1" (type "prepreg") (thickness 0.073) (material "FR4") (epsilon_r 4.3) (loss_tangent 0.02)) (layer "In1.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 2" (type "core") (thickness 0.12) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) (layer "In2.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 3" (type "prepreg") (thickness 0.195) (material "FR4") (epsilon_r 4.6) (loss_tangent 0.02) addsublayer (thickness 0.195)) (layer "In3.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 4" (type "core") (thickness 0.12) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) (layer "In4.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 5" (type "prepreg") (thickness 0.195) (material "FR4") (epsilon_r 4.6) (loss_tangent 0.02) addsublayer (thickness 0.195) (material "FR4") (epsilon_r 4.6) (loss_tangent 0.02) addsublayer (thickness 0) addsublayer (thickness 0)) (layer "In5.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 6" (type "core") (thickness 0.12) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) (layer "In6.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 7" (type "prepreg") (thickness 0.073) (material "FR4") (epsilon_r 4.3) (loss_tangent 0.02) addsublayer (thickness 0)) (layer "B.Cu" (type "copper") (thickness 0.035)) (layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01) (material "Epoxy") (epsilon_r 3.3) (loss_tangent 0)) (layer "B.Paste" (type "Bottom Solder Paste")) (layer "B.SilkS" (type "Bottom Silk Screen") (color "White")) (copper_finish "None") (dielectric_constraints no) )
The PCB stackup can be expanded with additional dielectric layers, as seen below, which will not be picked up by the parser.
TODO:
Possible test case: