Open CuteSC2 opened 2 years ago
revisions who some of them have huge differences of the Memory implementations
I am aware there are 4GB models but if the 8GB models have different memory implementations then that is a mess.
I don't believe Mellanox would have made DDR4 pinout alterations between revisions. That is too much hassle to keep track of and the board design is otherwise really well done. There are many subtleties to learn when trying to use the Innova-2's FPGA but they make sense in hindsight and speed up development. It is only the documentation that is lacking.
I am not aware of any way to probe the board revision from software. The end user needs to decide which Firmware and Bitstream to load onto a board.
There existing different Board revisions who some of them have huge differences of the Memory implementations.
PCB001842_01 (4GB Model)
PCB002310_00 (8GB Model)
PCB002319_00 (8GB Model)
[ ] Document differences in hardware Implementation
[ ] Document technical differences
[ ] Investigate if separate Bitstreams and Projects are needed for the 8GB models.