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myriadrf / LimeSuiteNG

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Changing LOFrequency in dualRXTX and calibration #22

Closed Jojeker closed 6 months ago

Jojeker commented 6 months ago

Hello,

we are performing some tests with the new limesuiteNG development branch on a LimeSDR XTRX. To this end, we execute the dualRXTX example which shows some output on our signal analyzer at 1.5GHz. However, if we change the frequencyLO variable to some other value in the allowed range (say 3.5GHz or 2.5GHz), then the output is not given.

We also noticed, that enabling the calibration on RX and TX does fail, but we could not figure out why this is the case. The error code that we retrieve upon debugging is: Rx ch%i DC/IQ calibration failed: %s leading to a segmentation fault in the example. Is this an error in limesuiteNG or is additional configuration required to perform successful calibration?

Thanks for your help!

We attach the logs for 1.5GHz and 3.5GHz below:

1.5 GHz:

sens@nuc4:~/Downloads/LimeSuiteNG/vbuild ./bin/examples/dualRXTX 
Devices found :
0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000

Configuring device ...
SetFrequencySXT, (1500.000 MHz)INT 111, FRAC 403298, DIV_LOCH 1, EN_DIV2_DIVPROG 1
Expected VCO 6000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=0
csw=124 cmphl=0
csw=126 cmphl=0
csw=127 cmphl=0
adjust with linear search:
CSW interval failed to lock
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=0
csw=176 cmphl=3
csw=168 cmphl=2
csw=172 cmphl=2
csw=174 cmphl=2
csw=175 cmphl=2
adjust with linear search:
csw=167 cmphl=0
CSW: lowest=168, highest=175, will use=171
choosing wider CSW locking range: low=168, high=175
TuneVCO(SXT) - confirmed lock with final csw=171, cmphl=2
VCOM : csw=171 tune ok
Tuning VCOH :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too high
VCOH : failed to lock
Selected: VCOM, CSW_VCO: 171
Sampling rate set(10.000 MHz): CGEN:80.000 MHz, Decim: 2^1, Interp: 2^1
INT 91, FRAC 322638, DIV_OUTCH_CGEN 14
VCO 2400.00 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 172; interval [169, 175]
FPGA::SetInterfaceFreq tx:20.000 MHz rx:20.000 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:20.000 MHz clockCount:2
CLK[0] Fout:20.000 MHz bypass:0 phase:114.26 findPhase: 0
CLK[1] Fout:20.000 MHz bypass:0 phase:114.26 findPhase: 1
FPGA PLL[1] M=64, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:20.000 MHz clockCount:2
CLK[0] Fout:20.000 MHz bypass:0 phase:95.03 findPhase: 0
CLK[1] Fout:20.000 MHz bypass:0 phase:95.03 findPhase: 1
FPGA PLL[0] M=64, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008
PLL Clock[1] PHCFG_START done
SDR configured in 843ms
StopStreaming
/dev/LimeXTRX0_trx0 usePoll:1 rxSamplesInPkt:256 rxPacketsInBatch:3, DMA_ReadSize:6192, batchSizeInTime:0us

Stream0 samplesInTxPkt:256 maxTxPktInBatch:3, batchSizeInTime:infus
StopStreaming
ResetTimestamp
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
StartStreaming
Stream started ...
/dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:9996288 pkt:39048 o:0(+0) l:0(+0) dma:13016/13020(4) swFIFO:0
Total samples received: 9997312  signal amplitude: 0.325509  total samples sent: 9997312
/dev/LimeXTRX0_trx0 Tx: 77.679 MB/s | TS:10061824 pkt:37866 o:0 shw:12622/12548(+74) u:396(+396) l:18(+18) tsAdvance:-74240/+60247/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:19998720 pkt:78120 o:0(+0) l:0(+0) dma:26040/26044(4) swFIFO:0
Total samples received: 19999744  signal amplitude: 0.283218  total samples sent: 19999744
/dev/LimeXTRX0_trx0 Tx: 80.645 MB/s | TS:20064256 pkt:76938 o:0 shw:25646/25573(+73) u:396(+0) l:18(+0) tsAdvance:+54784/+62758/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:29998080 pkt:117180 o:0(+0) l:0(+0) dma:39060/39064(4) swFIFO:1
Total samples received: 29997056  signal amplitude: 0.283389  total samples sent: 29997056
/dev/LimeXTRX0_trx0 Tx: 80.632 MB/s | TS:30061312 pkt:115989 o:0 shw:38663/38595(+68) u:396(+0) l:18(+0) tsAdvance:+52480/+62627/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:40000512 pkt:156252 o:0(+0) l:0(+0) dma:52084/52088(4) swFIFO:0
Total samples received: 40001536  signal amplitude: 0.28423  total samples sent: 40001536
/dev/LimeXTRX0_trx0 Tx: 80.645 MB/s | TS:40066816 pkt:155073 o:0 shw:51691/51616(+75) u:396(+0) l:18(+0) tsAdvance:+54784/+62693/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:50002176 pkt:195321 o:0(+0) l:0(+0) dma:65107/65108(1) swFIFO:1
Total samples received: 50002944  signal amplitude: 0.28424  total samples sent: 50002944
/dev/LimeXTRX0_trx0 Tx: 80.632 MB/s | TS:50068480 pkt:194142 o:0 shw:64714/64639(+75) u:396(+0) l:18(+0) tsAdvance:+42496/+62567/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 80.669 MB/s | TS:60002304 pkt:234384 o:0(+0) l:0(+0) dma:12592/12600(8) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 80.620 MB/s | TS:60067072 pkt:233199 o:0 shw:12197/12126(+71) u:396(+0) l:18(+0) tsAdvance:+54784/+62698/+64768, f:0
Total samples received: 60003328  signal amplitude: 0.284678  total samples sent: 60003328
/dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:70007808 pkt:273468 o:0(+0) l:0(+0) dma:25620/25620(0) swFIFO:5
/dev/LimeXTRX0_trx0 Tx: 80.657 MB/s | TS:70067968 pkt:272265 o:0 shw:25219/25147(+72) u:396(+0) l:18(+0) tsAdvance:+54016/+62719/+64768, f:0
Total samples received: 70007808  signal amplitude: 0.28273  total samples sent: 70007808
/dev/LimeXTRX0_trx0 Tx: 80.620 MB/s | TS:80070400 pkt:311337 o:0 shw:38243/38168(+75) u:396(+0) l:18(+0) tsAdvance:+54784/+62784/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:80007168 pkt:312528 o:0(+0) l:0(+0) dma:38640/38644(4) swFIFO:0
Total samples received: 80008192  signal amplitude: 0.28419  total samples sent: 80008192
/dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:90008064 pkt:351594 o:0(+0) l:0(+0) dma:51662/51664(2) swFIFO:1
Total samples received: 90007552  signal amplitude: 0.28566  total samples sent: 90007552
/dev/LimeXTRX0_trx0 Tx: 80.632 MB/s | TS:90072064 pkt:350406 o:0 shw:51266/51192(+74) u:396(+0) l:18(+0) tsAdvance:+53248/+62713/+64768, f:0
Rx0: packetsIn: 390615
/dev/LimeXTRX0_trx0 Tx: 73.357 MB/s | TS:100061440 pkt:389427 o:0 shw:64273/64273(+0) u:396(+0) l:18(+0) tsAdvance:+51712/+62663/+64768, f:0
StopStreaming
Tx Loop totals: packets sent: 389427 (0x0005F133) , FPGA packet counter: 389427 (0x0005F133), diff: 0, FPGA tx drops: 32
DeviceRegistry Removed: LitePCIe
DeviceRegistry Removed: FTDI
DeviceRegistry Removed: FX3

(For this one we notice that there is a DC bias, which does not always occur (i.e., power cycling solves this issue until it reoccurs).)

3.5 GHz:

sens@nuc4:~/Downloads/LimeSuiteNG/vbuild$ ./bin/examples/dualRXTX 
Devices found :
0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000

Configuring device ...
SetFrequencySXT, (3500.000 MHz)INT 130, FRAC 645277, DIV_LOCH 0, EN_DIV2_DIVPROG 1
Expected VCO 7000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOM : failed to lock
Tuning VCOH :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=2
csw=124 cmphl=2
csw=126 cmphl=2
csw=127 cmphl=2
adjust with linear search:
csw=119 cmphl=2
csw=118 cmphl=0
CSW: lowest=119, highest=127, will use=123
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=3
csw=144 cmphl=3
csw=136 cmphl=2
csw=140 cmphl=2
csw=142 cmphl=2
csw=143 cmphl=2
adjust with linear search:
csw=135 cmphl=2
csw=134 cmphl=2
csw=133 cmphl=2
csw=132 cmphl=2
csw=131 cmphl=2
csw=130 cmphl=2
csw=129 cmphl=2
csw=128 cmphl=2
CSW: lowest=128, highest=143, will use=135
CSW is locking in one continous range: low=119, high=143
TuneVCO(SXT) - confirmed lock with final csw=131, cmphl=2
VCOH : csw=131 tune ok
Selected: VCOH, CSW_VCO: 131
Sampling rate set(10.000 MHz): CGEN:80.000 MHz, Decim: 2^1, Interp: 2^1
INT 91, FRAC 322638, DIV_OUTCH_CGEN 14
VCO 2400.00 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 172; interval [169, 175]
FPGA::SetInterfaceFreq tx:20.000 MHz rx:20.000 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:20.000 MHz clockCount:2
CLK[0] Fout:20.000 MHz bypass:0 phase:114.26 findPhase: 0
CLK[1] Fout:20.000 MHz bypass:0 phase:114.26 findPhase: 1
FPGA PLL[1] M=64, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:20.000 MHz clockCount:2
CLK[0] Fout:20.000 MHz bypass:0 phase:95.03 findPhase: 0
CLK[1] Fout:20.000 MHz bypass:0 phase:95.03 findPhase: 1
FPGA PLL[0] M=64, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008
PLL Clock[1] PHCFG_START done
SDR configured in 853ms
StopStreaming
/dev/LimeXTRX0_trx0 usePoll:1 rxSamplesInPkt:256 rxPacketsInBatch:3, DMA_ReadSize:6192, batchSizeInTime:0us

Stream0 samplesInTxPkt:256 maxTxPktInBatch:3, batchSizeInTime:infus
StopStreaming
ResetTimestamp
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
StartStreaming
Stream started ...
/dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:9998592 pkt:39057 o:0(+0) l:0(+0) dma:13019/13020(1) swFIFO:11/dev/LimeXTRX0_trx0 Tx: 80.124 MB/s | TS:10053376 pkt:39018 o:0 shw:13006/12941(+65) u:0(+0) l:0(+0) tsAdvance:+36352/+60618/+64768, f:0

Total samples received: 9990144  signal amplitude: 0.373463  total samples sent: 9990144
/dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:19997952 pkt:78117 o:0(+0) l:0(+0) dma:26039/26040(1) swFIFO:3
/dev/LimeXTRX0_trx0 Tx: 80.626 MB/s | TS:20059648 pkt:78105 o:0 shw:26035/25962(+73) u:0(+0) l:0(+0) tsAdvance:+32512/+59868/+64768, f:1
Total samples received: 19996672  signal amplitude: 0.165747  total samples sent: 19996672
/dev/LimeXTRX0_trx0 Tx: 80.632 MB/s | TS:30059008 pkt:117165 o:0 shw:39055/38984(+71) u:0(+0) l:0(+0) tsAdvance:+48640/+60839/+64768, f:1
Total samples received: 29996032  signal amplitude: 0.165367  total samples sent: 29996032
/dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:29998080 pkt:117180 o:0(+0) l:0(+0) dma:39060/39064(4) swFIFO:2
/dev/LimeXTRX0_trx0 Tx: 80.626 MB/s | TS:40059904 pkt:156231 o:0 shw:52077/52005(+72) u:0(+0) l:0(+0) tsAdvance:+30208/+59809/+64768, f:0
Total samples received: 39996416  signal amplitude: 0.172751  total samples sent: 39996416
/dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:39999744 pkt:156249 o:0(+0) l:0(+0) dma:52083/52084(1) swFIFO:3
/dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:49997568 pkt:195303 o:0(+0) l:0(+0) dma:65101/65104(3) swFIFO:0
Total samples received: 49997824  signal amplitude: 0.163238  total samples sent: 49997824
/dev/LimeXTRX0_trx0 Tx: 80.626 MB/s | TS:50062336 pkt:195303 o:0 shw:65101/65029(+72) u:0(+0) l:0(+0) tsAdvance:+39424/+60189/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:59999232 pkt:234372 o:0(+0) l:0(+0) dma:12588/12592(4) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 80.626 MB/s | TS:60062464 pkt:234366 o:0 shw:12586/12517(+69) u:0(+0) l:0(+0) tsAdvance:+47104/+61063/+64768, f:2
Total samples received: 60000256  signal amplitude: 0.164881  total samples sent: 60000256
/dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:69998592 pkt:273432 o:0(+0) l:0(+0) dma:25608/25616(8) swFIFO:9
Total samples received: /dev/LimeXTRX0_trx0 Tx: 80.663 MB/s | TS:70055680 pkt:273402 o:0 shw:25598/25540(+58) u:0(+0) l:0(+0) tsAdvance:+39424/+59810/+64768, f:0
69992448  signal amplitude: 0.156581  total samples sent: 69992448
/dev/LimeXTRX0_trx0 Rx: 80.620 MB/s | TS:80000256 pkt:312501 o:0(+0) l:0(+0) dma:38631/38636(5) swFIFO:1
Total samples received: 80000000  signal amplitude: /dev/LimeXTRX0_trx0 Tx: 80.626 MB/s | TS:80063488 pkt:312495 o:0 shw:38629/38563(+66) u:0(+0) l:0(+0) tsAdvance:+47872/+60980/+64768, f:1
0.173769  total samples sent: 80000000
/dev/LimeXTRX0_trx0 Rx: 80.645 MB/s | TS:90003456 pkt:351576 o:0(+0) l:0(+0) dma:51656/51660(4) swFIFO:1
Total samples received: /dev/LimeXTRX0_trx0 Tx: 80.651 MB/s | TS:90068992 pkt:351579 o:0 shw:51657/51584(+73) u:0(+0) l:0(+0) tsAdvance:+40192/+61090/+64768, f:0
90005504  signal amplitude: 0.162127  total samples sent: 90005504
Rx0: packetsIn: 390624
/dev/LimeXTRX0_trx0 Tx: 73.301 MB/s | TS:100056064 pkt:390591 o:0 shw:64661/64661(+0) u:0(+0) l:0(+0) tsAdvance:+32512/+59499/+64768, f:0
StopStreaming
Tx Loop totals: packets sent: 390591 (0x0005F5BF) , FPGA packet counter: 390591 (0x0005F5BF), diff: 0, FPGA tx drops: 0
DeviceRegistry Removed: LitePCIe
DeviceRegistry Removed: FTDI
DeviceRegistry Removed: FX3
rjonaitis commented 6 months ago

I've fixed the crash caused by error message. The output signal power can change depending on LO frequency, so if you're not seeing the signal with higher LO frequencies, try increasing the gains. Calibration failure occurs due to too low gain settings, the algorithm expects that the set gains would be enough to achieve a certain signal power level over chip's internal loopback. If the gain is not enough, then calibration algorithm is not guaranteed to succeed. I've enabled debug level logging during calibration to provide more information of what's going on in there.

Jojeker commented 6 months ago

Thank you very much for your help! I appreciate the fast reply and your work in this matter! The 3.5 GHz example works now without problems.

I am a bit unsure about the "low gain settings" you mention: If I understand correctly then the gains have to be configured right at startup, i.e. by adding new values to the configuration. I adapted the example like this:

// RF parameters
    SDRConfig config;
    for (int c = 0; c < 2; ++c) // MIMO
    {
        config.channel[c].rx.enabled = true;
        config.channel[c].rx.centerFrequency = frequencyLO;
        config.channel[c].rx.gain[lime::eGainTypes::LNA] = 30;
        config.channel[c].rx.gain[lime::eGainTypes::PGA]  = 19;
        config.channel[c].rx.gain[lime::eGainTypes::TIA] = 12;
        config.channel[c].rx.sampleRate = sampleRate;
        config.channel[c].rx.oversample = 2;
        config.channel[c].rx.lpf = 0;
        config.channel[c].rx.path = 1; // TODO: replace with string names
        config.channel[c].rx.calibrate = true;

        config.channel[c].tx.enabled = true;
        config.channel[c].tx.gain[lime::eGainTypes::PAD] = 52;
        config.channel[c].tx.gain[lime::eGainTypes::IAMP] = 12;
        config.channel[c].tx.sampleRate = sampleRate;
        config.channel[c].tx.oversample = 2;
        config.channel[c].tx.path = 1; // TODO: replace with string names
        config.channel[c].tx.centerFrequency = frequencyLO;
        config.channel[c].tx.calibrate = false;
    }

To my knowledge all the gains I specify are the maximum of their respective ranges. Still, I run into the same issue when performing a calibration:

DeviceRegistry Added: FX3
DeviceRegistry Added: FTDI
DeviceRegistry Added: LitePCIe
Devices found :
0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000

Configuring device ...
SetFrequencySXR, (3500.000 MHz)INT 130, FRAC 645277, DIV_LOCH 0, EN_DIV2_DIVPROG 1
Expected VCO 7000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too low
VCOM : failed to lock
Tuning VCOH :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=2
csw=124 cmphl=2
csw=126 cmphl=2
csw=127 cmphl=2
adjust with linear search:
csw=119 cmphl=0
CSW: lowest=120, highest=127, will use=123
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=3
csw=144 cmphl=2
csw=152 cmphl=3
csw=148 cmphl=3
csw=146 cmphl=3
csw=145 cmphl=3
adjust with linear search:
csw=143 cmphl=2
csw=142 cmphl=2
csw=141 cmphl=2
csw=140 cmphl=2
csw=139 cmphl=2
csw=138 cmphl=2
csw=137 cmphl=2
csw=136 cmphl=2
csw=135 cmphl=2
csw=134 cmphl=2
csw=133 cmphl=2
csw=132 cmphl=2
csw=131 cmphl=2
csw=130 cmphl=2
csw=129 cmphl=2
csw=128 cmphl=2
CSW: lowest=128, highest=144, will use=136
CSW is locking in one continous range: low=120, high=144
TuneVCO(SXR) - confirmed lock with final csw=132, cmphl=2
VCOH : csw=132 tune ok
Selected: VCOH, CSW_VCO: 132
SetFrequencySXT, (3500.000 MHz)INT 130, FRAC 645277, DIV_LOCH 0, EN_DIV2_DIVPROG 1
Expected VCO 7000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOM : failed to lock
Tuning VCOH :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=2
csw=124 cmphl=2
csw=126 cmphl=2
csw=127 cmphl=2
adjust with linear search:
csw=119 cmphl=2
csw=118 cmphl=0
CSW: lowest=119, highest=127, will use=123
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=3
csw=144 cmphl=3
csw=136 cmphl=2
csw=140 cmphl=2
csw=142 cmphl=2
csw=143 cmphl=2
adjust with linear search:
csw=135 cmphl=2
csw=134 cmphl=2
csw=133 cmphl=2
csw=132 cmphl=2
csw=131 cmphl=2
csw=130 cmphl=2
csw=129 cmphl=2
csw=128 cmphl=2
CSW: lowest=128, highest=143, will use=135
CSW is locking in one continous range: low=119, high=143
TuneVCO(SXT) - confirmed lock with final csw=131, cmphl=2
VCOH : csw=131 tune ok
Selected: VCOH, CSW_VCO: 131
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 160; interval [157, 164]
RxLPF modifying G_PGA_RBB 31 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=0, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 160; interval [157, 164]
RxLPF modifying G_PGA_RBB 31 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=0, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
Sampling rate set(10.000 MHz): CGEN:80.000 MHz, Decim: 2^1, Interp: 2^1
INT 91, FRAC 322638, DIV_OUTCH_CGEN 14
VCO 2400.00 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 173; interval [170, 176]
Rx calibrate ch.A @ 3500 MHz, BW: 10 MHz, RF input: LNAH, PGA: 12, LNA: 15, TIA: 3
Rx DC auto   I:  -9, Q:  61, -43.4 dBFS
Rx DC manual I: -11, Q:  59, -58.9 dBFS
RxTSP DC corrector enabled -64.4 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -76.172 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 62 | -32.101 dbFS
Signal strength (-32.1 dBFS) low, expected to be more than (-30.0 dBFS), loopback not working?
Rx calibration failed
Rx ch0 DC/IQ calibration failed: Loopback signal weak: not connected/insufficient gain?
Rx calibrate ch.B @ 3500 MHz, BW: 10 MHz, RF input: LNAH, PGA: 12, LNA: 15, TIA: 3
Rx DC auto   I: -17, Q:  63, -30.6 dBFS
Rx DC manual I: -17, Q:  63, -30.6 dBFS
RxTSP DC corrector enabled -69.0 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -78.267 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 62 | -36.883 dbFS
Signal strength (-36.9 dBFS) low, expected to be more than (-30.0 dBFS), loopback not working?
Rx calibration failed
Rx ch1 DC/IQ calibration failed: Loopback signal weak: not connected/insufficient gain?
FPGA::SetInterfaceFreq tx:20.000 MHz rx:20.000 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:20.000 MHz clockCount:2
CLK[0] Fout:20.000 MHz bypass:0 phase:114.26 findPhase: 0
CLK[1] Fout:20.000 MHz bypass:0 phase:114.26 findPhase: 1
FPGA PLL[1] M=64, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:20.000 MHz clockCount:2
CLK[0] Fout:20.000 MHz bypass:0 phase:95.03 findPhase: 0
CLK[1] Fout:20.000 MHz bypass:0 phase:95.03 findPhase: 1
FPGA PLL[0] M=64, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008
PLL Clock[1] PHCFG_START done
SDR configured in 1508ms
StopStreaming

Am I missing some settings for the gains and their configuration? Any resource or help on understanding the process is appreciated!

Thanks again!

rjonaitis commented 6 months ago

It seems you're pretty close to the expected level Signal strength (-32.1 dBFS) low, expected to be more than (-30.0 dBFS). I've changed https://github.com/myriadrf/LimeSuiteNG/commit/ef80511924a77b0ba38a47aa1fec536abfb18aba the hard limit when the calibration would be aborted. Now it will still print a warning, but will continue to finish the prodecure.

Jojeker commented 6 months ago

Thanks for the update! I think this should fix the issue, I will try it out and update this thread as soon as possible. Is the low signal strength dependent of the hardware?

In addition, we were experimenting with the sampling frequency (e.g. 20MHz) in the dualRXTX example and found out that there is unexpected behavior when configuring the PLL clock 1 of TX:

We notice that RX works fine in any case, i.e., its PLL can be configured in any case regardless of the sampling frequency, while this is not the case with TX: There the PLL clock 1 is reporting some error in register 0x0021 and setting the error bits to 0x0008.

We used the provided documentation for the XTRX gateware from LimeSDR-XTRX_GW/doc/LimeSDR-XTRX_1v2_GW_User_Manual_v1.00.pdf at master · myriadrf/LimeSDR-XTRX_GW but could not follow the output. Are we messing up with lookup in the reference?

DeviceRegistry Added: FX3
DeviceRegistry Added: FTDI
DeviceRegistry Added: LitePCIe
Devices found :
0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000

Configuring device ...
SetFrequencySXR, (3500.000 MHz)INT 130, FRAC 645277, DIV_LOCH 0, EN_DIV2_DIVPROG 1
Expected VCO 7000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too low
VCOM : failed to lock
Tuning VCOH :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=2
csw=124 cmphl=2
csw=126 cmphl=2
csw=127 cmphl=2
adjust with linear search:
csw=119 cmphl=0
CSW: lowest=120, highest=127, will use=123
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=3
csw=144 cmphl=3
csw=136 cmphl=2
csw=140 cmphl=2
csw=142 cmphl=2
csw=143 cmphl=2
adjust with linear search:
csw=135 cmphl=2
csw=134 cmphl=2
csw=133 cmphl=2
csw=132 cmphl=2
csw=131 cmphl=2
csw=130 cmphl=2
csw=129 cmphl=2
csw=128 cmphl=2
CSW: lowest=128, highest=143, will use=135
CSW is locking in one continous range: low=120, high=143
TuneVCO(SXR) - confirmed lock with final csw=131, cmphl=2
VCOH : csw=131 tune ok
Selected: VCOH, CSW_VCO: 131
SetFrequencySXT, (3500.000 MHz)INT 130, FRAC 645277, DIV_LOCH 0, EN_DIV2_DIVPROG 1
Expected VCO 7000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOM : failed to lock
Tuning VCOH :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=2
csw=124 cmphl=2
csw=126 cmphl=2
csw=127 cmphl=2
adjust with linear search:
csw=119 cmphl=2
csw=118 cmphl=2
csw=117 cmphl=0
CSW: lowest=118, highest=127, will use=122
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=3
csw=144 cmphl=3
csw=136 cmphl=2
csw=140 cmphl=2
csw=142 cmphl=2
csw=143 cmphl=2
adjust with linear search:
csw=135 cmphl=2
csw=134 cmphl=2
csw=133 cmphl=2
csw=132 cmphl=2
csw=131 cmphl=2
csw=130 cmphl=2
csw=129 cmphl=2
csw=128 cmphl=2
CSW: lowest=128, highest=143, will use=135
CSW is locking in one continous range: low=118, high=143
TuneVCO(SXT) - confirmed lock with final csw=130, cmphl=2
VCOH : csw=130 tune ok
Selected: VCOH, CSW_VCO: 130
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 161; interval [157, 165]
RxLPF modifying G_PGA_RBB 31 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=0, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 160; interval [157, 163]
RxLPF modifying G_PGA_RBB 31 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=0, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
Sampling rate set(20.000 MHz): CGEN:160.000 MHz, Decim: 2^1, Interp: 2^1
INT 97, FRAC 483958, DIV_OUTCH_CGEN 7
VCO 2560.00 MHz, RefClk 26.00 MHz
ICT_VCO_CGEN: 16
csw 201; interval [198, 205]
Rx calibrate ch.A @ 3500 MHz, BW: 20 MHz, RF input: LNAW, PGA: 12, LNA: 15, TIA: 3
Rx DC auto   I:  35, Q:  63, -31.0 dBFS
Rx DC manual I:  34, Q:  63, -31.0 dBFS
RxTSP DC corrector enabled -34.3 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -75.012 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 62 | -30.519 dbFS
Signal strength (-30.5 dBFS) low, expected to be more than (-30.0 dBFS), loopback not working?
Rx calibration failed
Rx ch0 DC/IQ calibration failed: Loopback signal weak: not connected/insufficient gain?
Tx ch.A , BW: 20 MHz, RF output: BAND2, Gain: 63, loopb: internal
Rx DC auto   I:  34, Q:  63, -31.7 dBFS
Rx DC manual I:  26, Q:  63, -32.2 dBFS
RxTSP DC corrector enabled -76.8 dBFS
Receiver saturation search, target level: 20480 (-12.868 dBFS)
initial  PGA:  0, RXLOOPB:  7, -43.81 dbFS
adjusted PGA: 25, RXLOOPB: 15, -14.12 dBFS
Rx DC auto   I:  26, Q:  63, -6.8 dBFS
Rx DC manual I:  26, Q:  63, -6.9 dBFS
RxTSP DC corrector enabled -56.0 dBFS
#0 Tx DC manual I: -216, Q:  136, -50.9 dBFS
#1 Tx DC manual I: -272, Q:  200, -59.6 dBFS
#2 Tx DC manual I: -280, Q:  202, -59.5 dBFS
#0 Tx IQCORR: -128, -35.6 dBFS
#1 Tx GAIN_I: 1541, -44.3 dBFS
#2 Tx IQCORR: -144, -46.5 dBFS
Tx | DC   | GAIN | PHASE
---+------+------+------
I: | -280 | 1541 | -144
Q: |  202 | 2047 |
Calibrate Tx duration: 463 ms
Rx calibrate ch.B @ 3500 MHz, BW: 20 MHz, RF input: LNAW, PGA: 12, LNA: 15, TIA: 3
Rx DC auto   I:   0, Q:  63, -21.2 dBFS
Rx DC manual I:  -8, Q:  63, -21.9 dBFS
RxTSP DC corrector enabled -71.5 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -78.267 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 62 | -33.836 dbFS
Signal strength (-33.8 dBFS) low, expected to be more than (-30.0 dBFS), loopback not working?
Rx calibration failed
Rx ch1 DC/IQ calibration failed: Loopback signal weak: not connected/insufficient gain?
Tx ch.B , BW: 20 MHz, RF output: BAND2, Gain: 63, loopb: internal
Rx DC auto   I:  -8, Q:  63, -28.9 dBFS
Rx DC manual I:  -6, Q:  63, -28.9 dBFS
RxTSP DC corrector enabled -78.3 dBFS
Receiver saturation search, target level: 20480 (-12.868 dBFS)
initial  PGA:  0, RXLOOPB:  7, -47.21 dbFS
adjusted PGA: 25, RXLOOPB: 15, -17.27 dBFS
Rx DC auto   I:  -6, Q:  63, -5.3 dBFS
Rx DC manual I: -10, Q:  63, -5.6 dBFS
RxTSP DC corrector enabled -52.0 dBFS
#0 Tx DC manual I:  -25, Q:   16, -65.5 dBFS
#1 Tx DC manual I:  -28, Q:   30, -67.3 dBFS
#2 Tx DC manual I:  -20, Q:   23, -63.7 dBFS
#0 Tx IQCORR: 128, -40.9 dBFS
#1 Tx GAIN_Q: 1693, -43.8 dBFS
#2 Tx IQCORR: 144, -45.3 dBFS
Tx | DC   | GAIN | PHASE
---+------+------+------
I: |  -20 | 2047 | 144
Q: |   23 | 1693 |
Calibrate Tx duration: 467 ms
FPGA::SetInterfaceFreq tx:40.000 MHz rx:40.000 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:40.000 MHz clockCount:2
CLK[0] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 0
CLK[1] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
FPGA PLL[1] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:40.000 MHz clockCount:2
CLK[0] Fout:40.000 MHz bypass:0 phase:90 findPhase: 0
CLK[1] Fout:40.000 MHz bypass:0 phase:90 findPhase: 1
FPGA PLL[0] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START error, reg:0x0021=0x000D, errorBits:0x0008
PLL Clock[1] PHCFG_START done
SDR configured in 1848ms
StopStreaming
/dev/LimeXTRX0_trx0 usePoll:1 rxSamplesInPkt:256 rxPacketsInBatch:3, DMA_ReadSize:6192, batchSizeInTime:0us

Stream0 samplesInTxPkt:256 maxTxPktInBatch:3, batchSizeInTime:infus
StopStreaming
ResetTimestamp
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
StartStreaming
Stream started ...
Total samples received: 19997696  signal amplitude: 0.03898  total samples sent: 19997696
/dev/LimeXTRX0_trx0 Tx: 160.763 MB/s | TS:20061952 pkt:78114 o:0 shw:26038/25964(+74) u:0(+0) l:0(+0) tsAdvance:+54016/+62865/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:19998720 pkt:78120 o:0(+0) l:0(+0) dma:26040/26044(4) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 161.252 MB/s | TS:40062208 pkt:156240 o:0 shw:52080/52006(+74) u:0(+0) l:0(+0) tsAdvance:+40960/+62878/+64768, f:0
Total samples received: 39998464  signal amplitude: 0.0380264  total samples sent: 39998464
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:40000512 pkt:156252 o:0(+0) l:0(+0) dma:52084/52088(4) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 161.252 MB/s | TS:60062464 pkt:234366 o:0 shw:12586/12512(+74) u:0(+0) l:0(+0) tsAdvance:+53248/+63064/+64768, f:0
Total samples received: 59999232  signal amplitude: 0.0410621  total samples sent: 59999232
/dev/LimeXTRX0_trx0 Rx: 161.240 MB/s | TS:60002304 pkt:234384 o:0(+0) l:0(+0) dma:12592/12592(0) swFIFO:2

Thanks again for the help!

rjonaitis commented 6 months ago

Have you done any modifications to the code, outside of the example code? In your log I see the PLL[0] clock phase value (90) is not the same as mine (100.45).

FPGA SetPllFrequency: PLL[0] input:40.000 MHz clockCount:2
CLK[0] Fout:40.000 MHz bypass:0 phase:90 findPhase: 0
CLK[1] Fout:40.000 MHz bypass:0 phase:90 findPhase: 1
Jojeker commented 6 months ago

You are right, sorry for the confusion! We tried to get an understanding of the SetPllFrequency call and wanted to know, whether the phase was the issue. This is why we changed the value that resulted in the phase of 90 you reported.

We have rerun the code without any modifications and provide the output below: The code of the dualRXTX is as follows:

/**
    @file   dualRXTX.cpp
    @author Lime Microsystems (www.limemicro.com)
    @brief  minimal RX loopback to Tx example
 */
#include "limesuiteng/limesuiteng.hpp"
#include <iostream>
#include <chrono>
#include <string_view>
#include <cmath>
#include <signal.h>
#ifdef USE_GNU_PLOT
    #include "gnuPlotPipe.h"
#endif

using namespace lime;
using namespace std::literals::string_view_literals;

static const double frequencyLO = 1.5e9;
float sampleRate = 40e6;
static uint8_t chipIndex = 0; // device might have several RF chips

bool stopProgram(false);
void intHandler(int dummy)
{
    std::cout << "Stoppping\n"sv;
    stopProgram = true;
}

static LogLevel logVerbosity = LogLevel::Debug;
static void LogCallback(LogLevel lvl, const std::string& msg)
{
    if (lvl > logVerbosity)
        return;
    std::cout << msg << std::endl;
}

int main(int argc, char** argv)
{
    lime::registerLogHandler(LogCallback);
    auto handles = DeviceRegistry::enumerate();
    if (handles.size() == 0)
    {
        std::cout << "No devices found\n"sv;
        return -1;
    }
    std::cout << "Devices found :"sv << std::endl;
    for (size_t i = 0; i < handles.size(); i++)
        std::cout << i << ": "sv << handles[i].Serialize() << std::endl;
    std::cout << std::endl;

    // Use first available device
    SDRDevice* device = DeviceRegistry::makeDevice(handles.at(0));
    if (!device)
    {
        std::cout << "Failed to connect to device"sv << std::endl;
        return -1;
    }
    device->SetMessageLogCallback(LogCallback);
    device->Init();

    // RF parameters
    SDRConfig config;
    for (int c = 0; c < 2; ++c) // MIMO
    {
        config.channel[c].rx.enabled = true;
        config.channel[c].rx.centerFrequency = frequencyLO;
    config.channel[c].rx.gain[lime::eGainTypes::LNA] = 30;
        config.channel[c].rx.gain[lime::eGainTypes::PGA]  = 12;
        config.channel[c].rx.gain[lime::eGainTypes::TIA] = 5;
        config.channel[c].rx.sampleRate = sampleRate;
        config.channel[c].rx.oversample = 2;
        config.channel[c].rx.lpf = 0;
        config.channel[c].rx.path = 2; // TODO: replace with string names
        config.channel[c].rx.calibrate = true;

        config.channel[c].tx.enabled = true;
    config.channel[c].tx.gain[lime::eGainTypes::PAD] = 42;
        config.channel[c].tx.gain[lime::eGainTypes::IAMP] = 6;
        config.channel[c].tx.sampleRate = sampleRate;
        config.channel[c].tx.oversample = 2;
        config.channel[c].tx.path = 2; // TODO: replace with string names
        config.channel[c].tx.centerFrequency = frequencyLO;
        config.channel[c].tx.calibrate = true;
    }

    // Samples data streaming configuration
    StreamConfig stream;

    stream.channels[TRXDir::Rx] = { 0, 1 };
    stream.channels[TRXDir::Tx] = { 0, 1 };

    stream.format = DataFormat::F32;
    stream.linkFormat = DataFormat::I16;

    signal(SIGINT, intHandler);

    const int samplesInBuffer = 256 * 4;
    complex32f_t** rxSamples = new complex32f_t*[2]; // allocate two channels for simplicity
    for (int i = 0; i < 2; ++i)
        rxSamples[i] = new complex32f_t[samplesInBuffer];

#ifdef USE_GNU_PLOT
    GNUPlotPipe gp;
    gp.write("set size square\n set xrange[-1:1]\n set yrange[-1:1]\n");
#endif

    std::cout << "Configuring device ...\n"sv;
    try
    {
        auto t1 = std::chrono::high_resolution_clock::now();
        device->Configure(config, chipIndex);
        auto t2 = std::chrono::high_resolution_clock::now();
        std::cout << "SDR configured in "sv << std::chrono::duration_cast<std::chrono::milliseconds>(t2 - t1).count() << "ms\n"sv;

        device->StreamSetup(stream, chipIndex);
        device->StreamStart(chipIndex);

    } catch (std::runtime_error& e)
    {
        std::cout << "Failed to configure settings: "sv << e.what() << std::endl;
        return -1;
    } catch (std::logic_error& e)
    {
        std::cout << "Failed to configure settings: "sv << e.what() << std::endl;
        return -1;
    }
    std::cout << "Stream started ...\n"sv;

    auto startTime = std::chrono::high_resolution_clock::now();
    auto t1 = startTime;
    auto t2 = t1;

    int totalSamplesReceived = 0;
    uint32_t totalSamplesSent = 0;
    float maxSignalAmplitude = 0;

    StreamMeta rxMeta;
    while (std::chrono::high_resolution_clock::now() - startTime < std::chrono::seconds(10) && !stopProgram)
    {
        uint32_t samplesRead = device->StreamRx(chipIndex, rxSamples, samplesInBuffer, &rxMeta);
        totalSamplesReceived += samplesRead;

        // process samples
        for (uint32_t n = 0; n < samplesRead; ++n)
        {
            float amplitude = pow(rxSamples[0][n].real(), 2) + pow(rxSamples[0][n].imag(), 2);
            if (amplitude > maxSignalAmplitude)
                maxSignalAmplitude = amplitude;
        }

        StreamMeta txMeta;
        txMeta.timestamp = rxMeta.timestamp + samplesInBuffer * 64;
        txMeta.waitForTimestamp = true;
        txMeta.flushPartialPacket = false;
        uint32_t samplesSent = device->StreamTx(chipIndex, rxSamples, samplesInBuffer, &txMeta);
        if (samplesSent < 0)
        {
            std::cout << "Failure to send\n"sv;
            break;
        }
        totalSamplesSent += samplesSent;

        t2 = std::chrono::high_resolution_clock::now();
        if (t2 - t1 > std::chrono::seconds(1))
        {
            t1 = t2;
            std::cout << "Total samples received: "sv << totalSamplesReceived << "  signal amplitude: "sv
                      << std::sqrt(maxSignalAmplitude) << "  total samples sent: "sv << totalSamplesSent << std::endl;

#ifdef USE_GNU_PLOT
            gp.write("plot '-' with points title 'ch 0'");
            for (std::size_t c = 1; c < stream.channels.at(TRXDir::Rx).size(); ++c)
                gp.writef(", '-' with points title 'ch %i'\n", c);
            for (std::size_t c = 0; c < stream.channels.at(TRXDir::Rx).size(); ++c)
            {
                for (uint32_t n = 0; n < samplesInBuffer; ++n)
                    gp.writef("%f %f\n", rxSamples[c][n].real(), rxSamples[c][n].imag());
                gp.write("e\n");
                gp.flush();
            }
#endif
            maxSignalAmplitude = 0;
        }
    }
    DeviceRegistry::freeDevice(device);

    for (int i = 0; i < 2; ++i)
        delete[] rxSamples[i];
    delete[] rxSamples;
    return 0;
}
DeviceRegistry Added: FX3
DeviceRegistry Added: FTDI
DeviceRegistry Added: LitePCIe
Devices found :
0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000

Configuring device ...
SetFrequencySXR, (1500.000 MHz)INT 111, FRAC 403298, DIV_LOCH 1, EN_DIV2_DIVPROG 1
Expected VCO 6000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=0
csw=124 cmphl=0
csw=126 cmphl=0
csw=127 cmphl=0
adjust with linear search:
CSW interval failed to lock
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=0
csw=176 cmphl=3
csw=168 cmphl=0
csw=172 cmphl=2
csw=174 cmphl=2
csw=175 cmphl=2
adjust with linear search:
csw=171 cmphl=2
csw=170 cmphl=2
csw=169 cmphl=2
csw=168 cmphl=0
CSW: lowest=169, highest=175, will use=172
choosing wider CSW locking range: low=169, high=175
TuneVCO(SXR) - confirmed lock with final csw=172, cmphl=2
VCOM : csw=172 tune ok
Tuning VCOH :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too high
VCOH : failed to lock
Selected: VCOM, CSW_VCO: 172
SetFrequencySXT, (1500.000 MHz)INT 111, FRAC 403298, DIV_LOCH 1, EN_DIV2_DIVPROG 1
Expected VCO 6000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=0
csw=124 cmphl=0
csw=126 cmphl=0
csw=127 cmphl=0
adjust with linear search:
CSW interval failed to lock
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=0
csw=176 cmphl=3
csw=168 cmphl=2
csw=172 cmphl=2
csw=174 cmphl=2
csw=175 cmphl=2
adjust with linear search:
csw=167 cmphl=0
CSW: lowest=168, highest=175, will use=171
choosing wider CSW locking range: low=168, high=175
TuneVCO(SXT) - confirmed lock with final csw=171, cmphl=2
VCOM : csw=171 tune ok
Tuning VCOH :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too high
VCOH : failed to lock
Selected: VCOM, CSW_VCO: 171
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
csw 160; interval [157, 164]
RxLPF modifying G_PGA_RBB 24 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=1, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
csw 160; interval [157, 164]
RxLPF modifying G_PGA_RBB 24 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=1, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
Sampling rate set(40.000 MHz): CGEN:320.000 MHz, Decim: 2^1, Interp: 2^1
INT 97, FRAC 483958, DIV_OUTCH_CGEN 3
VCO 2560.00 MHz, RefClk 26.00 MHz
csw 202; interval [199, 205]
Rx calibrate ch.A @ 1500 MHz, BW: 40 MHz, RF input: LNAW, PGA: 12, LNA: 15, TIA: 1
Rx DC auto   I: -12, Q: -24, -44.1 dBFS
Rx DC manual I: -17, Q: -31, -75.0 dBFS
RxTSP DC corrector enabled -76.8 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -59.540 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 62 | -12.028 dbFS
#0 Rx IQCORR: -18, -50.9 dBFS
#1 Rx GAIN_Q: 2001, -81.0 dBFS
#2 Rx IQCORR: -18, -80.0 dBFS
Rx | DC   | GAIN | PHASE
---+------+------+------
I: |  -17 | 2047 | -18
Q: |  -15 | 2001 |
Calibrate Rx duration: 245 ms
Tx ch.A , BW: 40 MHz, RF output: BAND2, Gain: 63, loopb: internal
Rx DC auto   I: -17, Q: -31, -33.8 dBFS
Rx DC manual I: -10, Q: -23, -37.5 dBFS
RxTSP DC corrector enabled -82.2 dBFS
Receiver saturation search, target level: 20498 (-12.860 dBFS)
initial  PGA:  0, RXLOOPB:  7, -20.65 dbFS
adjusted PGA:  3, RXLOOPB: 15, -12.02 dBFS
Rx DC auto   I: -10, Q: -23, -34.0 dBFS
Rx DC manual I: -11, Q: -15, -38.4 dBFS
RxTSP DC corrector enabled -76.8 dBFS
#0 Tx DC manual I: -122, Q:   49, -81.0 dBFS
#1 Tx DC manual I: -122, Q:   49, -77.5 dBFS
#2 Tx DC manual I: -119, Q:   50, -83.5 dBFS
#0 Tx IQCORR: 16, -46.0 dBFS
#1 Tx GAIN_I: 1904, -52.4 dBFS
#2 Tx IQCORR: 31, -58.1 dBFS
Tx | DC   | GAIN | PHASE
---+------+------+------
I: | -119 | 1904 | 31
Q: |   50 | 2047 |
Calibrate Tx duration: 323 ms
Rx calibrate ch.B @ 1500 MHz, BW: 40 MHz, RF input: LNAW, PGA: 12, LNA: 15, TIA: 1
Rx DC auto   I: -15, Q:  15, -55.2 dBFS
Rx DC manual I: -17, Q:  13, -69.6 dBFS
RxTSP DC corrector enabled -80.0 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -69.847 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 62 | -19.381 dbFS
#0 Rx IQCORR: 8, -78.3 dBFS
#1 Rx GAIN_I: 2043, -87.1 dBFS
#2 Rx IQCORR: 8, -89.6 dBFS
Rx | DC   | GAIN | PHASE
---+------+------+------
I: |  -15 | 2043 | 8
Q: |   13 | 2047 |
Calibrate Rx duration: 246 ms
Tx ch.B , BW: 40 MHz, RF output: BAND2, Gain: 63, loopb: internal
Rx DC auto   I: -17, Q:  13, -44.2 dBFS
Rx DC manual I: -11, Q:  19, -68.7 dBFS
RxTSP DC corrector enabled -83.5 dBFS
Receiver saturation search, target level: 20498 (-12.860 dBFS)
initial  PGA:  0, RXLOOPB:  7, -30.67 dbFS
adjusted PGA: 13, RXLOOPB: 15, -12.18 dBFS
Rx DC auto   I: -11, Q:  19, -37.2 dBFS
Rx DC manual I: -15, Q:  17, -55.6 dBFS
RxTSP DC corrector enabled -71.5 dBFS
#0 Tx DC manual I:  -84, Q:   17, -75.0 dBFS
#1 Tx DC manual I:  -88, Q:   18, -80.0 dBFS
#2 Tx DC manual I:  -87, Q:   18, -79.1 dBFS
#0 Tx IQCORR: 27, -64.9 dBFS
#1 Tx GAIN_Q: 2030, -69.0 dBFS
#2 Tx IQCORR: 25, -75.6 dBFS
Tx | DC   | GAIN | PHASE
---+------+------+------
I: |  -87 | 2047 | 25
Q: |   18 | 2030 |
Calibrate Tx duration: 335 ms
FPGA::SetInterfaceFreq tx:80.000 MHz rx:80.000 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:80.000 MHz clockCount:2
CLK[0] Fout:80.000 MHz bypass:0 phase:188.66 findPhase: 0
CLK[1] Fout:80.000 MHz bypass:0 phase:188.66 findPhase: 1
FPGA PLL[1] M=16, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START error, reg:0x0021=0xFFFF, errorBits:0x0008
PLL Clock[1] PHCFG_START done
FPGA SetPllClock: failed to write registers
FPGA SetPllFrequency: PLL[0] input:80.000 MHz clockCount:2
CLK[0] Fout:80.000 MHz bypass:0 phase:111.29 findPhase: 0
CLK[1] Fout:80.000 MHz bypass:0 phase:111.29 findPhase: 1
FPGA PLL[0] M=16, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA SetPllClock: failed to write registers
SDR configured in 12997ms
StopStreaming
/dev/LimeXTRX0_trx0 usePoll:1 rxSamplesInPkt:256 rxPacketsInBatch:3, DMA_ReadSize:6192, batchSizeInTime:0us

Stream0 samplesInTxPkt:256 maxTxPktInBatch:3, batchSizeInTime:infus
StopStreaming
ResetTimestamp
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
StartStreaming
Stream started ...
/dev/LimeXTRX0_trx0 Tx: 0.000 MB/s | TS:0 pkt:0 o:0 shw:0/0(+0) u:0(+0) l:0(+0) tsAdvance:+10000000000000000/+0/+0, f:0
/dev/LimeXTRX0_trx0 Rx: 0.000 MB/s | TS:0 pkt:0 o:0(+0) l:0(+0) dma:0/0(0) swFIFO:0
Total samples received: 0  signal amplitude: 0  total samples sent: 1024
/dev/LimeXTRX0_trx0 Rx: 0.000 MB/s | TS:0 pkt:0 o:0(+0) l:0(+0) dma:0/0(0) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 0.000 MB/s | TS:139701534372112 pkt:3 o:0 shw:1/1(+0) u:0(+0) l:0(+0) tsAdvance:+139701534372112/+139701534372112/+139701534372112, f:0
/dev/LimeXTRX0_trx0 Rx: 0.000 MB/s | TS:0 pkt:0 o:0(+0) l:0(+0) dma:0/0(0) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 0.006 MB/s | TS:139701534372112 pkt:3 o:0 shw:1/1(+0) u:0(+0) l:0(+0) tsAdvance:+10000000000000000/+0/+0, f:0
Total samples received: 0  signal amplitude: 0  total samples sent: 2048
/dev/LimeXTRX0_trx0 Rx: 0.000 MB/s | TS:0 pkt:0 o:0(+0) l:0(+0) dma:0/0(0) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 0.008 MB/s | TS:139701534372112 pkt:7 o:0 shw:3/3(+0) u:0(+0) l:0(+0) tsAdvance:+139701534372112/+139701534372496/+139701534372880, f:0
/dev/LimeXTRX0_trx0 Rx: 0.000 MB/s | TS:0 pkt:0 o:0(+0) l:0(+0) dma:0/0(0) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 0.000 MB/s | TS:139701534372112 pkt:7 o:0 shw:3/3(+0) u:0(+0) l:0(+0) tsAdvance:+10000000000000000/+0/+0, f:0
Total samples received: 0  signal amplitude: 0  total samples sent: 3072
/dev/LimeXTRX0_trx0 Rx: 0.000 MB/s | TS:0 pkt:0 o:0(+0) l:0(+0) dma:0/0(0) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 0.008 MB/s | TS:139701534372112 pkt:11 o:0 shw:5/5(+0) u:0(+0) l:0(+0) tsAdvance:+139701534372112/+139701534372496/+139701534372880, f:0
/dev/LimeXTRX0_trx0 Rx: 0.000 MB/s | TS:0 pkt:0 o:0(+0) l:0(+0) dma:0/0(0) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 0.000 MB/s | TS:139701534372112 pkt:11 o:0 shw:5/5(+0) u:0(+0) l:0(+0) tsAdvance:+10000000000000000/+0/+0, f:0
Total samples received: 0  signal amplitude: 0  total samples sent: 4096
/dev/LimeXTRX0_trx0 Rx: 0.000 MB/s | TS:0 pkt:0 o:0(+0) l:0(+0) dma:0/0(0) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 0.002 MB/s | TS:139701534372112 pkt:15 o:0 shw:7/6(+1) u:0(+0) l:0(+0) tsAdvance:+139701534372112/+139701534372496/+139701534372880, f:0
/dev/LimeXTRX0_trx0 Rx: 0.000 MB/s | TS:0 pkt:0 o:0(+0) l:0(+0) dma:0/0(0) swFIFO:0
/dev/LimeXTRX0_trx0 Tx: 0.000 MB/s | TS:139701534372112 pkt:15 o:0 shw:7/6(+1) u:0(+0) l:0(+0) tsAdvance:+10000000000000000/+0/+0, f:0
Total samples received: 0  signal amplitude: 0  total samples sent: 5120
Rx0: packetsIn: 0
/dev/LimeXTRX0_trx0 Tx: 0.000 MB/s | TS:139701534372112 pkt:19 o:0 shw:9/6(+3) u:0(+0) l:0(+0) tsAdvance:+139701534372112/+139701534372496/+139701534372880, f:0
StopStreaming
Tx Loop totals: packets sent: 19 (0x00000013) , FPGA packet counter: 4 (0x00000004), diff: 15, FPGA tx drops: 0
DeviceRegistry Removed: LitePCIe
DeviceRegistry Removed: FTDI
DeviceRegistry Removed: FX3
rjonaitis commented 6 months ago

what is your XTRX gateware version/revision? You can run limeDevice --full to see it.

Jojeker commented 6 months ago

My gateware and firmware versions are below:

sens@nuc4:~$ sudo limeDevice --full
Found 1 device(s) :
0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000
        Expansion name          : UNSUPPORTED
        Firmware version        : 1
        Gateware version        : 1
        Gateware revision       : 8
        Gateware target board   : LimeSDR XTRX
        Hardware version        : 0
        Protocol version        : 1
        Serial number           : 65535
        SPI slave devices       :
                                  FPGA
                                  LMS7002M
        Memory devices          :
                                  FPGA FLASH
        GPS Lock:
                GPS - Undefined
                Glonass - Undefined
                Galileo - Undefined
                Beidou - Undefined
rjonaitis commented 6 months ago

Your gateware is 1.8, current latest one is 1.9 with a likely fix of your problem (https://github.com/myriadrf/LimeSDR-XTRX_GW/commit/1834a1d747caa8256c224cd6d0396959cf51394e)

Download the latest gateware: https://github.com/myriadrf/LimeSDR-XTRX_GW/raw/master/bitstream/flash_programming_file.bin and write it to device: limeFLASH --device=XTRX --target="FPGA FLASH" flash_programming_file.bin then power cycle the board so it would load the new gateware (You most likely need to fully shutdown your PC, as simply rebooting still keeps the PCIe slot powered on, and the board would keep running without reloading gateware)

HaoxinSEU commented 6 months ago

Hi,

Thanks for pointing out the gateware problem!

We are trying to use JTAG and Vivado to write the gateware. However, Vivado cannot detect the board.

Our steps are:

We are wondering if we use the JTAG in a wrong way? Can you give us some hints on this?

Thanks so much!

rjonaitis commented 6 months ago

I only do software, so can't really help you with JTAG. I suggest you create a topic in https://discourse.myriadrf.org/

Jojeker commented 6 months ago

Thanks for your heads up and resources!

We were successful in applying the latest gateware version to the LimeSDR XTRX! Moreover, we were successful in running the example with LO frequencies of 1.5GHz, 1.8GHz, 1.9GHz.

However, we are not able to set the LO frequency to 2.0GHz or any other value higher than this. At least we don't see any output on a signal analyzer while we have one for the previous tests. The sampling rate is set to 20MHz, and configuring higher values seems to work. For 1.5GHz and 2.0GHz we attach the output logs, although they seem to be very similar.

1.5 GHz @ 20MHz

DeviceRegistry Added: FX3
DeviceRegistry Added: FTDI
DeviceRegistry Added: LitePCIe
Devices found :
0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000

Configuring device ...
SetFrequencySXR, (1500.000 MHz)INT 111, FRAC 403298, DIV_LOCH 1, EN_DIV2_DIVPROG 1
Expected VCO 6000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=0
csw=124 cmphl=0
csw=126 cmphl=0
csw=127 cmphl=0
adjust with linear search:
CSW interval failed to lock
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=0
csw=176 cmphl=3
csw=168 cmphl=0
csw=172 cmphl=2
csw=174 cmphl=2
csw=175 cmphl=2
adjust with linear search:
csw=171 cmphl=2
csw=170 cmphl=2
csw=169 cmphl=2
csw=168 cmphl=0
CSW: lowest=169, highest=175, will use=172
choosing wider CSW locking range: low=169, high=175
TuneVCO(SXR) - confirmed lock with final csw=172, cmphl=2
VCOM : csw=172 tune ok
Tuning VCOH :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too high
VCOH : failed to lock
Selected: VCOM, CSW_VCO: 172
SetFrequencySXT, (1500.000 MHz)INT 111, FRAC 403298, DIV_LOCH 1, EN_DIV2_DIVPROG 1
Expected VCO 6000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=0
csw=124 cmphl=0
csw=126 cmphl=0
csw=127 cmphl=0
adjust with linear search:
CSW interval failed to lock
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=0
csw=176 cmphl=3
csw=168 cmphl=2
csw=172 cmphl=2
csw=174 cmphl=2
csw=175 cmphl=2
adjust with linear search:
csw=167 cmphl=0
CSW: lowest=168, highest=175, will use=171
choosing wider CSW locking range: low=168, high=175
TuneVCO(SXT) - confirmed lock with final csw=171, cmphl=2
VCOM : csw=171 tune ok
Tuning VCOH :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too high
VCOH : failed to lock
Selected: VCOM, CSW_VCO: 171
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
csw 160; interval [157, 164]
RxLPF modifying G_PGA_RBB 31 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=0, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
csw 160; interval [157, 164]
RxLPF modifying G_PGA_RBB 31 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=0, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
Sampling rate set(20.000 MHz): CGEN:160.000 MHz, Decim: 2^1, Interp: 2^1
INT 97, FRAC 483958, DIV_OUTCH_CGEN 7
VCO 2560.00 MHz, RefClk 26.00 MHz
csw 202; interval [199, 205]
Rx calibrate ch.A @ 1500 MHz, BW: 20 MHz, RF input: LNAH, PGA: 12, LNA: 15, TIA: 3
Rx DC auto   I:   1, Q:   1, -45.3 dBFS
Rx DC manual I:  -3, Q:  -4, -54.5 dBFS
RxTSP DC corrector enabled -64.8 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -53.893 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 27 | -9.859 dbFS
#0 Rx IQCORR: -22, -47.1 dBFS
#1 Rx GAIN_Q: 1993, -69.8 dBFS
#2 Rx IQCORR: -20, -68.5 dBFS
Rx | DC   | GAIN | PHASE
---+------+------+------
I: |   -3 | 2047 | -20
Q: |    5 | 1993 |
Calibrate Rx duration: 244 ms
Tx ch.A , BW: 20 MHz, RF output: BAND1, Gain: 63, loopb: internal
Rx DC auto   I:  -3, Q:  -4, -48.9 dBFS
Rx DC manual I:  -8, Q:  -5, -67.1 dBFS
RxTSP DC corrector enabled -78.3 dBFS
Receiver saturation search, target level: 20498 (-12.860 dBFS)
initial  PGA:  0, RXLOOPB:  7, -19.62 dbFS
adjusted PGA:  2, RXLOOPB: 15, -11.95 dBFS
Rx DC auto   I:  -8, Q:  -5, -58.4 dBFS
Rx DC manual I:  -9, Q:  -4, -68.7 dBFS
RxTSP DC corrector enabled -74.5 dBFS
#0 Tx DC manual I: -160, Q:   64, -68.0 dBFS
#1 Tx DC manual I: -168, Q:   65, -77.5 dBFS
#2 Tx DC manual I: -166, Q:   63, -76.2 dBFS
#0 Tx IQCORR: 16, -43.6 dBFS
#1 Tx GAIN_I: 1791, -55.9 dBFS
#2 Tx IQCORR: 31, -69.6 dBFS
Tx | DC   | GAIN | PHASE
---+------+------+------
I: | -166 | 1791 | 31
Q: |   63 | 2047 |
Calibrate Tx duration: 405 ms
Rx calibrate ch.B @ 1500 MHz, BW: 20 MHz, RF input: LNAH, PGA: 12, LNA: 15, TIA: 3
Rx DC auto   I: -11, Q:  12, -52.3 dBFS
Rx DC manual I: -10, Q:  12, -68.2 dBFS
RxTSP DC corrector enabled -41.5 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -54.745 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 45 | -9.977 dbFS
#0 Rx IQCORR: 6, -69.0 dBFS
#1 Rx GAIN_Q: 2045, -72.2 dBFS
#2 Rx IQCORR: 6, -73.5 dBFS
Rx | DC   | GAIN | PHASE
---+------+------+------
I: |   -4 | 2047 | 6
Q: |   12 | 2045 |
Calibrate Rx duration: 268 ms
Tx ch.B , BW: 20 MHz, RF output: BAND1, Gain: 63, loopb: internal
Rx DC auto   I: -10, Q:  12, -37.6 dBFS
Rx DC manual I:  -2, Q:  20, -46.2 dBFS
RxTSP DC corrector enabled -77.5 dBFS
Receiver saturation search, target level: 20498 (-12.860 dBFS)
initial  PGA:  0, RXLOOPB:  7, -23.72 dbFS
adjusted PGA:  6, RXLOOPB: 15, -12.12 dBFS
Rx DC auto   I:  -2, Q:  20, -44.6 dBFS
Rx DC manual I:   5, Q:  20, -62.7 dBFS
RxTSP DC corrector enabled -74.0 dBFS
#0 Tx DC manual I: -112, Q:  -14, -76.2 dBFS
#1 Tx DC manual I: -112, Q:  -16, -80.0 dBFS
#2 Tx DC manual I: -112, Q:  -13, -78.3 dBFS
#0 Tx IQCORR: 20, -59.8 dBFS
#1 Tx GAIN_I: 2007, -71.5 dBFS
#2 Tx IQCORR: 23, -76.2 dBFS
Tx | DC   | GAIN | PHASE
---+------+------+------
I: | -112 | 2007 | 23
Q: |  -13 | 2047 |
Calibrate Tx duration: 414 ms
FPGA::SetInterfaceFreq tx:40.000 MHz rx:40.000 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:40.000 MHz clockCount:2
CLK[0] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 0
CLK[1] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
FPGA PLL[1] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:40.000 MHz clockCount:2
CLK[0] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 0
CLK[1] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 1
FPGA PLL[0] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
SDR configured in 1696ms
StopStreaming
/dev/LimeXTRX0_trx0 usePoll:1 rxSamplesInPkt:256 rxPacketsInBatch:3, DMA_ReadSize:6192, batchSizeInTime:0us

Stream0 samplesInTxPkt:256 maxTxPktInBatch:3, batchSizeInTime:infus
StopStreaming
ResetTimestamp
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
StartStreaming
Stream started ...
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:19998720 pkt:78120 o:0(+0) l:0(+0) dma:26040/26044(4) swFIFO:0
Total samples received: 19999744  signal amplitude: 0.0181454  total samples sent: 19999744
/dev/LimeXTRX0_trx0 Tx: 160.757 MB/s | TS:20064256 pkt:78123 o:0 shw:26041/25966(+75) u:0(+0) l:0(+0) tsAdvance:+61696/+63619/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:40000512 pkt:156252 o:0(+0) l:0(+0) dma:52084/52088(4) swFIFO:0
Total samples received: 40001536  signal amplitude: 0.0136806  total samples sent: 40001536
/dev/LimeXTRX0_trx0 Tx: 161.258 MB/s | TS:40066048 pkt:156255 o:0 shw:52085/52009(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63616/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:60002304 pkt:234384 o:0(+0) l:0(+0) dma:12592/12596(4) swFIFO:0
Total samples received: 60003328  signal amplitude: 0.0136719  total samples sent: 60003328
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:60067840 pkt:234387 o:0 shw:12593/12517(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63616/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:80004096 pkt:312516 o:0(+0) l:0(+0) dma:38636/38640(4) swFIFO:0
Total samples received: 80005120  signal amplitude: 0.0135052  total samples sent: 80005120
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:80069632 pkt:312519 o:0 shw:38637/38562(+75) u:0(+0) l:0(+0) tsAdvance:+47104/+63608/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:100005888 pkt:390648 o:0(+0) l:0(+0) dma:64680/64684(4) swFIFO:0
Total samples received: 100006912  signal amplitude: 0.0131836  total samples sent: 100006912
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:100071424 pkt:390651 o:0 shw:64681/64606(+75) u:0(+0) l:0(+0) tsAdvance:+61696/+63619/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:120007680 pkt:468780 o:0(+0) l:0(+0) dma:25188/25192(4) swFIFO:0
Total samples received: 120008704  signal amplitude: 0.0138107  total samples sent: 120008704
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:120073216 pkt:468783 o:0 shw:25189/25113(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63618/+64768, f:1
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:140009472 pkt:546912 o:0(+0) l:0(+0) dma:51232/51236(4) swFIFO:0
Total samples received: 140010496  signal amplitude: 0.0139908  total samples sent: 140010496
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:140075008 pkt:546915 o:0 shw:51233/51158(+75) u:0(+0) l:0(+0) tsAdvance:+61696/+63621/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:160011264 pkt:625044 o:0(+0) l:0(+0) dma:11740/11744(4) swFIFO:0
Total samples received: 160012288  signal amplitude: 0.0133364  total samples sent: 160012288
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:160076800 pkt:625047 o:0 shw:11741/11665(+76) u:0(+0) l:0(+0) tsAdvance:+60160/+63618/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:180013056 pkt:703176 o:0(+0) l:0(+0) dma:37784/37788(4) swFIFO:0
Total samples received: 180014080  signal amplitude: 0.013029  total samples sent: 180014080
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:180078592 pkt:703179 o:0 shw:37785/37709(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63621/+64768, f:0
Rx0: packetsIn: 781248
/dev/LimeXTRX0_trx0 Tx: 146.625 MB/s | TS:200061952 pkt:781239 o:0 shw:63805/63805(+0) u:0(+0) l:0(+0) tsAdvance:+61696/+63617/+64768, f:0
StopStreaming
Tx Loop totals: packets sent: 781239 (0x000BEBB7) , FPGA packet counter: 781239 (0x000BEBB7), diff: 0, FPGA tx drops: 0
DeviceRegistry Removed: LitePCIe
DeviceRegistry Removed: FTDI
DeviceRegistry Removed: FX3

2.0 GHz @ 20MHz (no output on signal analyzer)

DeviceRegistry Added: FX3
DeviceRegistry Added: FTDI
DeviceRegistry Added: LitePCIe
Devices found :
0: LimeXTRX0, media=PCIe, addr=/dev/LimeXTRX0_control, serial=0000000000000000

Configuring device ...
SetFrequencySXR, (1500.000 MHz)INT 111, FRAC 403298, DIV_LOCH 1, EN_DIV2_DIVPROG 1
Expected VCO 6000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=0
csw=124 cmphl=0
csw=126 cmphl=0
csw=127 cmphl=0
adjust with linear search:
CSW interval failed to lock
TuneVCO(SXR) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=0
csw=176 cmphl=3
csw=168 cmphl=0
csw=172 cmphl=2
csw=174 cmphl=2
csw=175 cmphl=2
adjust with linear search:
csw=171 cmphl=2
csw=170 cmphl=2
csw=169 cmphl=2
csw=168 cmphl=0
CSW: lowest=169, highest=175, will use=172
choosing wider CSW locking range: low=169, high=175
TuneVCO(SXR) - confirmed lock with final csw=172, cmphl=2
VCOM : csw=172 tune ok
Tuning VCOH :
TuneVCO(SXR) ICT_VCO: 192
TuneVCO(SXR) - attempted VCO too high
VCOH : failed to lock
Selected: VCOM, CSW_VCO: 172
SetFrequencySXT, (1500.000 MHz)INT 111, FRAC 403298, DIV_LOCH 1, EN_DIV2_DIVPROG 1
Expected VCO 6000.00 MHz, RefClk 26.00 MHz
Tuning VCOL :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too low
VCOL : failed to lock
Tuning VCOM :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - searching interval [0:128]
binary search:
csw=64  cmphl=0
csw=96  cmphl=0
csw=112 cmphl=0
csw=120 cmphl=0
csw=124 cmphl=0
csw=126 cmphl=0
csw=127 cmphl=0
adjust with linear search:
CSW interval failed to lock
TuneVCO(SXT) - searching interval [128:256]
binary search:
csw=192 cmphl=3
csw=160 cmphl=0
csw=176 cmphl=3
csw=168 cmphl=2
csw=172 cmphl=2
csw=174 cmphl=2
csw=175 cmphl=2
adjust with linear search:
csw=167 cmphl=0
CSW: lowest=168, highest=175, will use=171
choosing wider CSW locking range: low=168, high=175
TuneVCO(SXT) - confirmed lock with final csw=171, cmphl=2
VCOM : csw=171 tune ok
Tuning VCOH :
TuneVCO(SXT) ICT_VCO: 192
TuneVCO(SXT) - attempted VCO too high
VCOH : failed to lock
Selected: VCOM, CSW_VCO: 171
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
csw 160; interval [157, 164]
RxLPF modifying G_PGA_RBB 31 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=0, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
INT 88, FRAC 835634, DIV_OUTCH_CGEN 18
VCO 2334.72 MHz, RefClk 26.00 MHz
csw 160; interval [157, 164]
RxLPF modifying G_PGA_RBB 31 -> 12
RxLPF(0): TIA_C=0, TIA_RCOMP=15, TIA_CCOMP=0, RX_L_C=0, RX_H_C=0

RxLPF bypassed
TxLPF bypassed
Sampling rate set(20.000 MHz): CGEN:160.000 MHz, Decim: 2^1, Interp: 2^1
INT 97, FRAC 483958, DIV_OUTCH_CGEN 7
VCO 2560.00 MHz, RefClk 26.00 MHz
csw 202; interval [199, 205]
Rx calibrate ch.A @ 1500 MHz, BW: 20 MHz, RF input: LNAH, PGA: 12, LNA: 15, TIA: 3
Rx DC auto   I:   0, Q:   2, -47.2 dBFS
Rx DC manual I:  -3, Q:  -3, -56.5 dBFS
RxTSP DC corrector enabled -61.4 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -54.384 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 28 | -9.776 dbFS
#0 Rx IQCORR: -20, -46.2 dBFS
#1 Rx GAIN_Q: 1991, -66.6 dBFS
#2 Rx IQCORR: -22, -66.8 dBFS
Rx | DC   | GAIN | PHASE
---+------+------+------
I: |   -3 | 2047 | -22
Q: |    5 | 1991 |
Calibrate Rx duration: 238 ms
Tx ch.A , BW: 20 MHz, RF output: BAND1, Gain: 63, loopb: internal
Rx DC auto   I:  -3, Q:  -3, -48.1 dBFS
Rx DC manual I:  -7, Q:  -5, -67.3 dBFS
RxTSP DC corrector enabled -76.2 dBFS
Receiver saturation search, target level: 20498 (-12.860 dBFS)
initial  PGA:  0, RXLOOPB:  7, -19.75 dbFS
adjusted PGA:  2, RXLOOPB: 15, -12.06 dBFS
Rx DC auto   I:  -7, Q:  -5, -55.6 dBFS
Rx DC manual I:  -9, Q:  -4, -66.4 dBFS
RxTSP DC corrector enabled -75.0 dBFS
#0 Tx DC manual I: -168, Q:   72, -68.5 dBFS
#1 Tx DC manual I: -170, Q:   72, -69.0 dBFS
#2 Tx DC manual I: -165, Q:   64, -82.2 dBFS
#0 Tx IQCORR: 12, -43.5 dBFS
#1 Tx GAIN_I: 1791, -54.2 dBFS
#2 Tx IQCORR: 28, -64.9 dBFS
Tx | DC   | GAIN | PHASE
---+------+------+------
I: | -165 | 1791 | 28
Q: |   64 | 2047 |
Calibrate Tx duration: 400 ms
Rx calibrate ch.B @ 1500 MHz, BW: 20 MHz, RF input: LNAH, PGA: 12, LNA: 15, TIA: 3
Rx DC auto   I: -10, Q:  12, -66.2 dBFS
Rx DC manual I: -10, Q:  12, -67.1 dBFS
RxTSP DC corrector enabled -46.6 dBFS
Initial gains:  G_RXLOOPB:  2, CG_IAMP:  1 | -55.232 dBFS
Adjusted gains: G_RXLOOPB: 14, CG_IAMP: 48 | -9.895 dbFS
#0 Rx IQCORR: 0, -72.2 dBFS
#1 Rx GAIN_Q: 2045, -75.0 dBFS
#2 Rx IQCORR: 0, -74.5 dBFS
Rx | DC   | GAIN | PHASE
---+------+------+------
I: |   -4 | 2047 | 0
Q: |   12 | 2045 |
Calibrate Rx duration: 266 ms
Tx ch.B , BW: 20 MHz, RF output: BAND1, Gain: 63, loopb: internal
Rx DC auto   I: -10, Q:  12, -37.6 dBFS
Rx DC manual I:  -2, Q:  20, -46.2 dBFS
RxTSP DC corrector enabled -78.3 dBFS
Receiver saturation search, target level: 20498 (-12.860 dBFS)
initial  PGA:  0, RXLOOPB:  7, -23.01 dbFS
adjusted PGA:  5, RXLOOPB: 15, -12.38 dBFS
Rx DC auto   I:  -2, Q:  20, -44.3 dBFS
Rx DC manual I:   5, Q:  20, -65.3 dBFS
RxTSP DC corrector enabled -74.0 dBFS
#0 Tx DC manual I: -100, Q:  -12, -67.7 dBFS
#1 Tx DC manual I: -110, Q:  -15, -78.3 dBFS
#2 Tx DC manual I: -109, Q:  -16, -82.2 dBFS
#0 Tx IQCORR: 16, -61.3 dBFS
#1 Tx GAIN_I: 1999, -79.1 dBFS
#2 Tx IQCORR: 17, -80.0 dBFS
Tx | DC   | GAIN | PHASE
---+------+------+------
I: | -109 | 1999 | 17
Q: |  -16 | 2047 |
Calibrate Tx duration: 410 ms
FPGA::SetInterfaceFreq tx:40.000 MHz rx:40.000 MHz channel:0
FPGA SetPllFrequency: PLL[1] input:40.000 MHz clockCount:2
CLK[0] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 0
CLK[1] Fout:40.000 MHz bypass:0 phase:139.06 findPhase: 1
FPGA PLL[1] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[1] PLLCFG_START
FPGA PLL[1] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
FPGA SetPllFrequency: PLL[0] input:40.000 MHz clockCount:2
CLK[0] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 0
CLK[1] Fout:40.000 MHz bypass:0 phase:100.45 findPhase: 1
FPGA PLL[0] M=32, N=1, Fvco=1280.000 MHz (Requested 1280.000 MHz)
FPGA PLL[0] PLLCFG_START
FPGA PLL[0] PLLCFG_START done
PLL Clock[0] PHCFG_START
PLL Clock[0] PHCFG_START done
PLL Clock[1] PHCFG_START
PLL Clock[1] PHCFG_START done
SDR configured in 1661ms
StopStreaming
/dev/LimeXTRX0_trx0 usePoll:1 rxSamplesInPkt:256 rxPacketsInBatch:3, DMA_ReadSize:6192, batchSizeInTime:0us

Stream0 samplesInTxPkt:256 maxTxPktInBatch:3, batchSizeInTime:infus
StopStreaming
ResetTimestamp
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
SetOSThreadPriority: Failed to set priority(6), schec_prio(1), policy(1), ret(99)
StartStreaming
Stream started ...
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:19998720 pkt:78120 o:0(+0) l:0(+0) dma:26040/26044(4) swFIFO:0
Total samples received: 19999744  signal amplitude: 0.0203268  total samples sent: 19999744
/dev/LimeXTRX0_trx0 Tx: 160.751 MB/s | TS:20064256 pkt:78123 o:0 shw:26041/25965(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63616/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:40000512 pkt:156252 o:0(+0) l:0(+0) dma:52084/52088(4) swFIFO:0
Total samples received: 40001536  signal amplitude: 0.0136719  total samples sent: 40001536
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:40066048 pkt:156255 o:0 shw:52085/52009(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63617/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:60002304 pkt:234384 o:0(+0) l:0(+0) dma:12592/12596(4) swFIFO:0
Total samples received: 60003328  signal amplitude: 0.014427  total samples sent: 60003328
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:60067840 pkt:234387 o:0 shw:12593/12517(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63618/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:80004096 pkt:312516 o:0(+0) l:0(+0) dma:38636/38640(4) swFIFO:0
Total samples received: 80005120  signal amplitude: 0.0128447  total samples sent: 80005120
/dev/LimeXTRX0_trx0 Tx: 161.271 MB/s | TS:80069632 pkt:312519 o:0 shw:38637/38562(+75) u:0(+0) l:0(+0) tsAdvance:+50176/+63610/+64768, f:3
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:100005888 pkt:390648 o:0(+0) l:0(+0) dma:64680/64684(4) swFIFO:0
Total samples received: 100006912  signal amplitude: 0.0138796  total samples sent: 100006912
/dev/LimeXTRX0_trx0 Tx: 161.258 MB/s | TS:100071424 pkt:390651 o:0 shw:64681/64605(+76) u:0(+0) l:0(+0) tsAdvance:+54784/+63553/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:120007680 pkt:468780 o:0(+0) l:0(+0) dma:25188/25192(4) swFIFO:0
Total samples received: 120008704  signal amplitude: 0.014681  total samples sent: 120008704
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:120073216 pkt:468783 o:0 shw:25189/25113(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63617/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:140009472 pkt:546912 o:0(+0) l:0(+0) dma:51232/51236(4) swFIFO:0
Total samples received: 140010496  signal amplitude: 0.0140588  total samples sent: 140010496
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:140075008 pkt:546915 o:0 shw:51233/51157(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63617/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:160011264 pkt:625044 o:0(+0) l:0(+0) dma:11740/11744(4) swFIFO:0
Total samples received: 160012288  signal amplitude: 0.0141686  total samples sent: 160012288
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:160076800 pkt:625047 o:0 shw:11741/11665(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63616/+64768, f:0
/dev/LimeXTRX0_trx0 Rx: 161.264 MB/s | TS:180013056 pkt:703176 o:0(+0) l:0(+0) dma:37784/37788(4) swFIFO:0
Total samples received: 180014080  signal amplitude: 0.0134077  total samples sent: 180014080
/dev/LimeXTRX0_trx0 Tx: 161.264 MB/s | TS:180078592 pkt:703179 o:0 shw:37785/37709(+76) u:0(+0) l:0(+0) tsAdvance:+61696/+63616/+64768, f:0
Rx0: packetsIn: 781248
/dev/LimeXTRX0_trx0 Tx: 146.625 MB/s | TS:200061952 pkt:781239 o:0 shw:63805/63805(+0) u:0(+0) l:0(+0) tsAdvance:+61696/+63619/+64768, f:0
StopStreaming
Tx Loop totals: packets sent: 781239 (0x000BEBB7) , FPGA packet counter: 781239 (0x000BEBB7), diff: 0, FPGA tx drops: 0
DeviceRegistry Removed: LitePCIe
DeviceRegistry Removed: FTDI
DeviceRegistry Removed: FX3

If there is any other information to provide, we are happy to help!

rjonaitis commented 5 months ago

Try setting Tx output path to Band1 it should be better config.channel[c].tx.path = 1;

Jojeker commented 5 months ago

Thanks for the information! With the TX path configured to 1, we indeed see some peak on the signal analyzer during calibration. However, we after this stage, at least for frequencies at 3.5GHz LO frequency, we do not see any information.

Additionally, we also tried to do some tests where we submit some predefined samples that map to a certain frequency range, but we were unable to see the according output on the signal analyzer. Instead we see seldom peaks.

Moreover, we looked into the data sheet of the LMS7002 and want to make sure that we got it right:

Thanks for the help!

rjonaitis commented 5 months ago

I would need to see the code that you used to send the samples, or did you use limeTRX command line interface?

As for the hardware capabilities, data sheets, and configuration recommendations please ask about them in the https://discourse.myriadrf.org/ as I'm not deeply familiar with them, so I can't recomend what settings you should be running for particular scenarios. In addition threads in the forum will be visible for everyone, so if anyone would have the same issues they could find the answers there.