Closed Shimogawa closed 1 week ago
Hi, thanks for taking the time to engage with the IDE and report this!
However, based on the book, the correct address width here is indeed 14.
Generally, the address width will be log2(n)
where n
is the RAM size.
Here is the relevant slide from the lectures:
Please reopen this if you feel anything is lacking in my response
Oops, thanks for pointing that out. I think I have mistaken it as 32K. Sorry about this.
Tool
Hardware Simulator
Interface
Website (https://nand2tetris.github.io/web-ide)
Contact Details
No response
What happened?
https://github.com/nand2tetris/web-ide/blob/91d029938f1daa22cc2c31c5fe3c6dd7e47df6b2/projects/src/project_03/08_ram16k.ts#L12
The width of the address input here should be 15 instead of 14.
Additional Comments
No response
Do you want to try to fix this bug?
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