Add missing begin token, document the active low input pins - Githubissues

nandland / spi-slave

SPI Slave for FPGA in Verilog and VHDL

MIT License

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Add missing begin token, document the active low input pins #1

Closed pbsds closed 2 years ago

pbsds commented 5 years ago

Neither Vivado nor Yosys was able to parse it