Open zzattack opened 2 years ago
GowinSynthesis reports an implicit latch at https://github.com/nandland/spi-slave/blob/e12af3489df78d30dd745b00d163a3848bdcea69/Verilog/source/SPI_Slave.v#L167
WARN (DI0003) : Latch inferred for net 'r_SPI_MISO_Bit';We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("spi_slave.v":167)
GowinSynthesis reports an implicit latch at https://github.com/nandland/spi-slave/blob/e12af3489df78d30dd745b00d163a3848bdcea69/Verilog/source/SPI_Slave.v#L167
WARN (DI0003) : Latch inferred for net 'r_SPI_MISO_Bit';We do not recommend the use of latches in FPGA designs, as they may lead to timing problems("spi_slave.v":167)