A method of detecting when the slave finished serializing a bit on MISO should be added.

nandland / spi-slave

SPI Slave for FPGA in Verilog and VHDL

MIT License

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A method of detecting when the slave finished serializing a bit on MISO should be added. #13

Open OmarAmer01 opened 6 months ago

OmarAmer01 commented 6 months ago

Since the controller (FPGA) and SPI work on different clock domains, the controller needs to know when it can send another byte on MISO to avoid causing buffer overruns.