Warning: Async reset value `\r_TX_Byte [7]' is not constant!

[TCWilliamson]

Hi,

I've been trying to get this library to work on an Ice40 FPGA with Icestorm,

it -really- doesn't want to work thanks to the ' or posedge i_SPI_CS_n' of line 154. On removal, it will compile, but then comms is wrong, likely due to the CS triggering at the wrong time.

Is there a possibility of a fix on this?

yosys -p "synth_ice40 -blif hardware.blif" -q comm_fpga_spi.v main.v
Warning: Yosys has only limited support for tri-state logic at the moment. (comm_fpga_spi.v:194)
Warning: reg '\o_SPI_MISO' is assigned in a continuous assignment at comm_fpga_spi.v:194.
Warning: Async reset value `\r_TX_Byte [7]' is not constant!
arachne-pnr -d 5k -P sg48 -p up5k.pcf -o hardware.asc -q hardware.blif
hardware.blif:116: fatal error: unknown model `$_DFFSR_PPP_'
scons: *** [hardware.asc] Error 1

[grahamjonesgs]

Hi, I am using a different toolchain and FPGA (using VIVADO and a BASYS 3 board). I noticed this would not compile as a "begin" statement was needed here around line 156. "begin" is needed between the lines (to match the end two lines later):-

   if (i_SPI_CS_n)
      r_TX_Bit_Count <= 3'b111;  // Send MSb first

The it compiled and worked.

Good luck!