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nandland / spi-slave

SPI Slave for FPGA in Verilog and VHDL
MIT License
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Fixed some (3) errors #6

Open LeSpirou opened 3 years ago

LeSpirou commented 3 years ago

Changed "o_SPI_MISO" from register to net (line 37) due to combinatorical assignment (line 195). Fixed typo in sensitivity list (line 138), from w_SPI_CLK to w_SPI_Clk. Synthesis error: Added begin statement after if block (line 157).