Open nbstrong opened 2 years ago
There are no checks in the hardware for violating RHW.
After a read enable high, the controller should wait at least 200 ns before asserting write enable low.
This can be reproduced in simulation by reading the id and then reading parameter page.
This has been bypassed by adding a wait in testbench and software.
A hardware fix should be done, though.
There are no checks in the hardware for violating RHW.
After a read enable high, the controller should wait at least 200 ns before asserting write enable low.
This can be reproduced in simulation by reading the id and then reading parameter page.