Trying to count the number of inverters

[Mbonea-Mjema]

Hello,

I am trying to count the number of inverters in an MIG network is it possible?

[zfchu]

Hi,

That's possibile.

also> read_aiger c17.aig also> convert --aig_to_mig //aig to mig also> convert --mig_to_xmg // note here mig is one-to-one mapped to xmg, acturally still an MIG also> xmgcost // report the status [i] Gates = 7 [i] Num MAJs = 6 [i] Num XORs = 1 [i] Inverters = 4 [i] Depth (def.) = 2 [i] Depth mixed = 3 [i] Depth mixed (MAJ) = 2 [i] Depth mixed (INV) = 1 [i] Depth mixed (XOR) = 0 [i] Dangling inputs = 11 [i] QCA (area) = 0.03 um^2 [i] QCA (delay) = 0.02 ns [i] QCA (energy) = 63.46 E-21 J

Hope it helps.

[Mbonea-Mjema]

Thanks, it's very helpful, is there also a way to get the connection of the gates ? (The resulting graph)

[zfchu]

Hi,

we support writing dot files for visualization and verilog files for other processes.

Continue with the example: also> write_dot -x -f c17.dot // write the dot file also> write_verilog -x c17.v //write the verilog file also> quit

Then you can use dot (GraphViz software) to draw a picture. As an example: dot -Tpng c17.dot -o c17.png open c17.png

[Mbonea-Mjema]

One last thing, the formula used to calculate the energy and delay, do you have any references that I may read to better understand them.

Maybe this could be another issue, but I noticed that I get a 'segmentation fault' error when loading some of the EPFL benchmarks circuits (Divisor, multiplier, square-root, square, round robin arbiter and memory controller).

[zfchu]

1, Please refer to Chu, Z., Shi, L., Wang, L., & Xia, Y. (2019). Multi-objective algebraic rewriting in XOR-majority graphs. Integration, 69, 40-49, for details and related reference.

2, Can you please post the command line for the 'segmentation fault', as I cannot reproduce the error.

also> read_aiger ~/benchmarks/aiger/epfl/div.aig also> ps -a AIG i/o = 128/128 gates = 57247 level = 4372 also> convert --aig_to_mig

Works find on my machine.

[Mbonea-Mjema]

Thank you for the reference paper, can the tool be used for Majority 5 as well?

I am running it on an online temporary VPS (Gitpod)

[zfchu]

In terms of reading issue, please consider pull the master to keep it update.

also> read_aiger ~/Downloads/sqrt.aig also> ps -a AIG i/o = 128/64 gates = 24618 level = 5058 also>

It works fine on my MAC.

ALSO can be also used for majority 5.

also> load 1234 also> exact_m5ig [i] 3 steps are required [expressions] f=<00a!cd> g=<!abcc!d> h=<!b!cfgg> [time]: 10.94 seconds

One can read a truth table 0x1234 to obtain a majority 5 logic expressions.

[Mbonea-Mjema]

Can I use the majority 5 on the benchmarks?

[zfchu]

Please pull the master and rebuild.

also> read_aiger c17.aig also> lut_mapping also> lut_resyn -nr also> ps -r M5IG i/o = 5/2 gates = 4 level = 2 also> write_bench -r c17_m5ig.bench also> write_dot -r -f c17.dot also> quit

[Mbonea-Mjema]

Hi again, I have a few questions.. 1.Is there a configuration which provides the best cost result (area) ? 2.Is there a configuration which provides the best depth result ?

[zfchu]

Hi

Currently, we cannot provide an optimal result since lots of algorithms are heuristic. But you can try different optimization scripts. Indeed, there are some AI-driven logic synthesis work to help find a good script.

[Mbonea-Mjema]

Hi,

In the paper "Multi-objective algebraic rewriting in XOR-majority graphs" a depth optimized area_aware algorithm (algorithm 2) was described... I would be grateful to at least be able to get the results form that algorithm.

Thanks for the help

[zfchu]

Hi

I just revisit the paper and try to reproduce the experiment results. Note that the algorithms and methods implemented in ALSO and mockturtle library are on-growing, if you really want exactly the same results, it woule be possibile to download an old version of ALSO, e.g., the version at the very beginning.

Otherwise, just type the commands:

read_aiger xx.aiger; lut_mapping; lut_resyn -nx -k 4; ps -x; xmgrw -a; ps -x

May it helps.

[Mbonea-Mjema]

Thanks for everything

[Mbonea-Mjema]

Hello,

I was trying to get the xmg circuit from the verilog file, I noticed that the number of inverters are more than the number I got from the xmgcost command, I tried this with the EPFL benchmarks. I also tried to use xmginv to optimize the number of inverters, but I got the same verilog file in the output as before the inverter optimization.

without the xmginv

    read_aiger $i; ps -a;
    lut_mapping;
    convert --aig_to_mig; ps -m;
    convert --mig_to_xmg; ps -x;
   write_verilog -x $destination_path/${strarr[5]}.v;

with the xmginv

    read_aiger $i; ps -a;
    lut_mapping;
    convert --aig_to_mig; ps -m;
    convert --mig_to_xmg; ps -x;
    xmginv
    write_verilog -x $destination_path/${strarr[5]}.v;