nczempin / NICNAC16-FPGA

Learning CPU design with an old-school 16-bit FPGA implementation
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(Basys 3) map 32 pmod lines to memory and i/o #55

Open nczempin opened 4 years ago

nczempin commented 4 years ago

16 data lines 12 address lines 4 lines for rotary switch?

nczempin commented 4 years ago

I don't have enough lines for both memory-mapped and programmed i/o.

nczempin commented 4 years ago

I can reduce the 4 lines for the switch to 2 lines.

I need some lines for talking to the memory.

Presumably I can reuse (multiplex) address lines for I/O