nematoli / SPI-FPGA-VHDL

SPI Master and Slave components to be used in all of FPGAs, written in VHDL.
GNU General Public License v3.0
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aggregate error at spi_slave.vhd(50): choice must be constant #1

Open Skytrobb opened 5 years ago

Skytrobb commented 5 years ago

I get this error during compilation, I'm not quite sure what it means. Am I incorrectly initializing the entity?

Also, I'm trying to use my Altera DE0_CV as a slave device to talk to an Arduino Master device. Is this even possible?

chipher-zero commented 1 year ago

Using an arty A7 I ran into the same problem. I substituted the process with the following and it worked fine-ish. At least the synthesis was successful. Now my problem is that it only seems to receive data HIGH (nothing but ones at the rx port)

PROCESS(ss_n, clk) BEGIN IF(ss_n = '1' OR reset_n = '0') THEN
bit_counter <= (others => '0'); if cpha = '1' then bit_counter(0) <= '1'; else bit_counter(1) <= '1'; end if; --reset active bit binary_read ELSE
IF(rising_edge(clk)) THEN
bit_counter <= bit_counter(data_length-1 DOWNTO 0) & '0'; --left shift active bit indicator END IF; END IF; END PROCESS;