PCB Final Refinements - Githubissues

[x] Make 20mil traces for power ground
[x] Add another polygon for inductor near PMIC, high switching
[x] L5 also add polygon, fix the polygon
[x] All 90 need teardrops, no acute angles
[x] Crystal internal connections make it 6mil
[x] Decap C6 placement near connector is not on path
[x] Get the two pin crystal closer if possible
[x] ESD diode for reset button is wrong
[x] Cross Unders too big, it's better to have many small cross Unders than have a big cut in the ground plane
[x] Add one missing via on the antenna
[x] Patch return path with two vias on top layer near debugger
[x] Have multiple smaller cross unders than one big one
[x] Do not cross under the RF trace at all
[x] Vias on Pads
[x] Keep important things on the path
[x] D5 should be in the path,
[x] Try to put individual grounds
[x] Connect SoC ground next to feed line to ground on shielding
[x] Debugger around traces don't need to go around
[x] Make sure all tolerances are right between components and traces.
[x] Top layer big cross unders
[x] Decaps are wrong in many places
[x] Placement of D6 is wrong, follow circuit placement
[x] Connect power lines around not in-between BME280
[x] C9 placement?

neohere97 / SkySync