Closed Gaurav5566 closed 2 years ago
Hi! The transistor width 19.74F is the access transistor size by calculation (#200-201 in SubArray.cpp)
cell.resCellAccess = cell.resistanceOn IR_DROP_TOLERANCE; //calculate access CMOS resistance cell.widthAccessCMOS = CalculateOnResistance(tech.featureSize, NMOS, inputParameter.temperature, tech) LINEAR_REGION_RATIO / cell.resCellAccess; //get access CMOS width
When your Ron is low, the resistance of the access transistor has also to be low to avoid obvious IR drop, therefore its width has to be large. To solve this problem, you need to enlarge the assigned cell width in layout or enlarge the resistanceOn.
I have used the following parameters for 1T1R cell (STT-MRAM)
But I am getting the following error while performing inference simulation: Transistor width of 1T1R=19.74F is larger than the assigned cell width=6.00F in layout