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neurosim / DNN_NeuroSim_V1.3

Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
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Transistor width of 1T1R=19.74F is larger than the assigned cell width=6.00F in layout #25

Closed Gaurav5566 closed 2 years ago

Gaurav5566 commented 2 years ago

I have used the following parameters for 1T1R cell (STT-MRAM)

/*** parameters for analog synaptic devices ***/
heightInFeatureSize1T1R = 6;        // 1T1R Cell height in feature size
widthInFeatureSize1T1R = 5.5;         // 1T1R Cell width in feature size
heightInFeatureSizeCrossbar = 2;    // Crossbar Cell height in feature size
widthInFeatureSizeCrossbar = 2;     // Crossbar Cell width in feature size
   resistanceOn = 3.5e3;               // Ron resistance at Vr in the reported measurement data (need to recalculate below if considering the nonlinearity)
resistanceOff = 8e3;           // Roff resistance at Vr in the reported measurement data (need to recalculate below if considering the nonlinearity)

But I am getting the following error while performing inference simulation: Transistor width of 1T1R=19.74F is larger than the assigned cell width=6.00F in layout

neurosim commented 2 years ago

Hi! The transistor width 19.74F is the access transistor size by calculation (#200-201 in SubArray.cpp)

cell.resCellAccess = cell.resistanceOn IR_DROP_TOLERANCE; //calculate access CMOS resistance cell.widthAccessCMOS = CalculateOnResistance(tech.featureSize, NMOS, inputParameter.temperature, tech) LINEAR_REGION_RATIO / cell.resCellAccess; //get access CMOS width

When your Ron is low, the resistance of the access transistor has also to be low to avoid obvious IR drop, therefore its width has to be large. To solve this problem, you need to enlarge the assigned cell width in layout or enlarge the resistanceOn.