search

neurosim / DNN_NeuroSim_V1.3

Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
62 stars 36 forks source link

Confilict in power consumption #9

Closed msabri1372 closed 2 years ago

msabri1372 commented 3 years ago

Hello, I am using DNN_NeuroSim for inference part. I am unable to find correct relation between Power consumption and Chip area.For instance, in the NeuroSim, for pretrained VGG8 the power consumption and Chip area are around 0.1 Watt and 120 mm2. Howover, in the same platforms such as ISAAC and PUMA-simulator the power consumption and Chip area are around 65 Watt and 90 mm2. I can not understant this difference. Please help me.

PUMA-simulator: https://github.com/Aayush-Ankit/puma-simulator ISAAC paper: https://www.cs.utah.edu/~rajeev/pubs/isca16.pdf

neurosim commented 3 years ago

Hi! Did you use the same memory device settings for every simulator? And the architecture and circuit assumptions of different simulators also might be different and affect the results. I think you might have to make every setting as similar as possible for fair comparison between different simulators.

msabri1372 commented 3 years ago

Hi! Thank you for your reply. I have changed all the possible configuration but the power consumption and the area does not have reasonable correlations.For instance for VGG8, in the 22nm technology, Power consumption and area overhead for RRAM (input and wieght precision is 8-bit, memory cell precision is 2-bit and ADC precision is 4 bit ) are 27mW and 45.5 mm2 respectively that these results aren't reasonable and the power consumption should be so much higher. Please help me to understand this relation better.

neurosim commented 3 years ago

Hi! I think our power estimation is reasonable. You can check a recent review paper of us

S. Yu, H. Jiang, S. Huang, X. Peng, A. Lu, “Compute-in-memory chips for deep learning: recent trends and prospects”, IEEE Circuits and Systems Magazine, vol. 21, no. 3, pp. 31-56, 2021.

We surveyed some RRAM-based CIM designs in Table 2 and they all show <1mW each subarray. The 22nm example (ISSCC' 20) shows only 0.06mW, then the whole chip power of tens of mW is reasonable.

I think you reference the 65W from the ISAAC paper. In their table 1, it shows the power of each IMA unit is 289/12=24mW, and most of which are from ADC of 16mW. However, actually, 8-bit ADC consumes only tens of uW in most designs. The ISAAC paper did brilliant and pioneer work on CIM architecture, but I personally think their circuit estimation is kind of rough.