Open neuschaefer opened 3 years ago
Currently under review on the mailing lists.
Did you have a feedback ?
I need it for the mmc0: sdhci@b0007000
.
I haven't checked back with the mailing lists in a while, sorry. Not sure when I'll get around to it again
Edit (2024-03-10): I've sent another version of the patchset today
Write a driver for the clock controller, which also handles resets.
The wiki page also needs a bit more substance.Current issues
adcdiv
) aren't correctly parented anymore, thus freq=0clk_hw_register_divider_table_parent_data
doesn't passnp
to__clk_hw_register_divider
, but it would be useless anyway,np
isn't used there.dev
toclk_hw_register_divider_table_parent_data
etc. because there is not device. That's why fw_name doesn't work.clk_parent_data::index
doesn't work like I expected, at all