The relative phase between the target clock and the ADC sampling clock phase is not always consistent when scope.clock.adc_mul is changed, or when the frequency of scope.clock.clkgen_src is changed.
Running scope.clock.pll.recal() and re-setting scope.clock.clkgen_src appears to resolve the problem but more testing is needed.
The relative phase between the target clock and the ADC sampling clock phase is not always consistent when
scope.clock.adc_mulis changed, or when the frequency ofscope.clock.clkgen_srcis changed.Running
scope.clock.pll.recal()and re-settingscope.clock.clkgen_srcappears to resolve the problem but more testing is needed.