The I2C bus to pins 3 (RPH_G2_SDA) and 5 (RPH_G3_SCL) does not have on-board pull-up resistors but with Raspberry Pi HATs it is the responsibility of the controller SoC (Sonata FPGA) to provide bus termination when these pins are used as I2C rather than GPIO. Probing the Raspberry Pi 4 when driving the Sense HAT indicates the presence of pull ups, whilst no such resistors are present on the HATs themselves.
I2C pull-up resistors are typically 1.8k to 3.3k, and whilst the weak internal pull-ups of the FPGA pins may be enabled, these offer a resistance of between 10k and 37k (calculated from the Xilinx Artix-7 datasheet).
Experimentally, on one particular board enabling the internal pull-ups is sufficient to operate in Standard-mode (100kbit/s), but the SI starts to fall apart below Fast-mode (400kbit/s). (Aside: It does function with current I2C test software, but this may be only because the bit rate is actually around 290kbit/s with the current settings calculated by the software.)
With external pull-up resistors present (3.3k and 5.1k because they were to hand), operation up to Fast-mode Plus is possible (though, again this is a claimed 1Mbit/s, but actual measurements presently indicate 590kbit/s)
The two images above show Standard-mode operation (100kbit/s) and the longer rise time - although not especially marked - can be seen.
The I2C bus to pins 3 (RPH_G2_SDA) and 5 (RPH_G3_SCL) does not have on-board pull-up resistors but with Raspberry Pi HATs it is the responsibility of the controller SoC (Sonata FPGA) to provide bus termination when these pins are used as I2C rather than GPIO. Probing the Raspberry Pi 4 when driving the Sense HAT indicates the presence of pull ups, whilst no such resistors are present on the HATs themselves.
I2C pull-up resistors are typically 1.8k to 3.3k, and whilst the weak internal pull-ups of the FPGA pins may be enabled, these offer a resistance of between 10k and 37k (calculated from the Xilinx Artix-7 datasheet).
Experimentally, on one particular board enabling the internal pull-ups is sufficient to operate in Standard-mode (100kbit/s), but the SI starts to fall apart below Fast-mode (400kbit/s). (Aside: It does function with current I2C test software, but this may be only because the bit rate is actually around 290kbit/s with the current settings calculated by the software.)
With external pull-up resistors present (3.3k and 5.1k because they were to hand), operation up to Fast-mode Plus is possible (though, again this is a claimed 1Mbit/s, but actual measurements presently indicate 590kbit/s)
The two images above show Standard-mode operation (100kbit/s) and the longer rise time - although not especially marked - can be seen.