Add multi-FPGA support for RT engine using feature toggles

[buckd]

• [X] This contribution adheres to CONTRIBUTING.md.

What does this Pull Request accomplish?

Enables custom device engine to handle multiple FPGAs for a single APU. Note there is no implementation of the multi-FPGA in the engine yet, this is just the infrastructure/wrappers.

Why should this Pull Request be merged?

Multiple FPGAs are needed in order to test engine setups that require more channels than a single R Series board can provide.

What testing has been done?

Verified single FPGA case still works as it did previously since the old code path is maintained.

[buckd]

A lot of these files changed because the location of one of the typedefs moved in a previous commit. There were no code changes outside the project file, Engine Simulation Tooklit Engine.lvlib, newly added VIs and the following existing VIs.

• RT Driver VI.vi
• Initialize ESTE.vi
• Close all FPGA refs.vi

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Engine Simulation Toolkit Engine.lvlib--Analog Replay 1.0 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--Analog Replay 1.0 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--APU 1.0 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--APU 1.0 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--APU 1.1 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--APU 1.1 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--APU 1.3 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--APU 1.3 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--Close all FPGA refs.vi.png:

Engine Simulation Toolkit Engine.lvlib--Close FPGA Refs - Multi FPGA.vi.png:

Engine Simulation Toolkit Engine.lvlib--Close FPGA Refs - Single FPGA.vi.png:

Engine Simulation Toolkit Engine.lvlib--Digital Pattern Gen 1.0 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--Digital Pattern Gen 1.0 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--Digital Pattern Gen 1.3 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--Digital Pattern Gen 1.3 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--Directional Speed 1.0 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--Directional Speed 1.0 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--Event Timing Capture 1.0 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--Event Timing Capture 1.0 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--Event Timing Measure 1.0 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--Event Timing Measure 1.0 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--Event Timing Measure 1.1 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--Event Timing Measure 1.1 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--Execute Engine - Multi FPGA.vi.png:

Engine Simulation Toolkit Engine.lvlib--Execute Engine - Single FPGA.vi.png:

Engine Simulation Toolkit Engine.lvlib--Execute Engine Wrapper.vi.png:

Engine Simulation Toolkit Engine.lvlib--Init Bitfile.vi.png:

Engine Simulation Toolkit Engine.lvlib--Init Unused IP.vi.png:

Engine Simulation Toolkit Engine.lvlib--Initialize Engine - Multi FPGA.vi.png:

Engine Simulation Toolkit Engine.lvlib--Initialize Engine - Single FPGA.vi.png:

Engine Simulation Toolkit Engine.lvlib--Initialize ESTE.vi.png:

Engine Simulation Toolkit Engine.lvlib--Knock Cylinder 1.0 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--Knock Cylinder 1.0 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--Knock Sensor 1.0 Init.vi.png:

Engine Simulation Toolkit Engine.lvlib--Knock Sensor 1.0 Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--Read VS FIFO.vi.png:

Engine Simulation Toolkit Engine.lvlib--RT Driver VI.vi.png:

Engine Simulation Toolkit Engine.lvlib--Run Bitfile.vi.png:

Engine Simulation Toolkit Engine.lvlib--Status Run.vi.png:

Engine Simulation Toolkit Engine.lvlib--Write VS FIFO.vi.png: