Add copies of 3 ECAT APIs used by the FPGA Page - Local.vi to the repo:
niECATCreateIOVStructureFromBitfile.vi
niECATGetCustomIOVNodeArrayFrom2009Bitfile.vi
niECATGetCustomIOVNodeArrayFrom2010Bitfile.vi
Link to these copies instead of the EtherCAT driver contents of vi.lib
All changes and re-linking were done on a VM with LabVIEW 2019 and dependencies installed except for EtherCAT.
Why should this Pull Request be merged?
This is prep work for building the custom device with LabVIEW 2021 and no EtherCAT and cRIO support for 64-bit. This change stands on its own and allows FPGA Page - Local.vi to be built as part of the System Explorer build with LabVIEW 2021 64-bit.
What testing has been done?
Built System Explorer spec on a VM with LabVIEW 2019 and dependencies installed except for EtherCAT.
(I had to also remove Action VIs broken by lack of ECAT and cRIO, but these changes will come later when 2021 build support is enabled)
SEECD Engine.lvlib--Compare Modules.vi.png
![capture](https://raw.githubusercontent.com/niveristand-diff-bot/diff-images/master/NI/niveristand-scan-engine-ethercat-custom-device/PR-180/2021-10-14/18%3A22%3A01/SEECD%20Engine.lvlib--Compare%20Modules.vi.png)SEECD System Explorer.lvlib--Get FPGA Info.vi.png
![capture](https://raw.githubusercontent.com/niveristand-diff-bot/diff-images/master/NI/niveristand-scan-engine-ethercat-custom-device/PR-180/2021-10-14/18%3A22%3A01/SEECD%20System%20Explorer.lvlib--Get%20FPGA%20Info.vi.png)SEECD System Explorer.lvlib--Host - Firmware Download.vi.png
![capture](https://raw.githubusercontent.com/niveristand-diff-bot/diff-images/master/NI/niveristand-scan-engine-ethercat-custom-device/PR-180/2021-10-14/18%3A22%3A01/SEECD%20System%20Explorer.lvlib--Host%20-%20Firmware%20Download.vi.png)SEECD System Explorer.lvlib--niECATCreateIOVStructureFromBitfile.vi.png
![capture](https://raw.githubusercontent.com/niveristand-diff-bot/diff-images/master/NI/niveristand-scan-engine-ethercat-custom-device/PR-180/2021-10-14/18%3A22%3A01/SEECD%20System%20Explorer.lvlib--niECATCreateIOVStructureFromBitfile.vi.png)SEECD System Explorer.lvlib--niECATGetCustomIOVNodeArrayFrom2009Bitfile.vi.png
![capture](https://raw.githubusercontent.com/niveristand-diff-bot/diff-images/master/NI/niveristand-scan-engine-ethercat-custom-device/PR-180/2021-10-14/18%3A22%3A01/SEECD%20System%20Explorer.lvlib--niECATGetCustomIOVNodeArrayFrom2009Bitfile.vi.png)SEECD System Explorer.lvlib--niECATGetCustomIOVNodeArrayFrom2010Bitfile.vi.png
![capture](https://raw.githubusercontent.com/niveristand-diff-bot/diff-images/master/NI/niveristand-scan-engine-ethercat-custom-device/PR-180/2021-10-14/18%3A22%3A01/SEECD%20System%20Explorer.lvlib--niECATGetCustomIOVNodeArrayFrom2010Bitfile.vi.png)
What does this Pull Request accomplish?
All changes and re-linking were done on a VM with LabVIEW 2019 and dependencies installed except for EtherCAT.
Why should this Pull Request be merged?
This is prep work for building the custom device with LabVIEW 2021 and no EtherCAT and cRIO support for 64-bit. This change stands on its own and allows
FPGA Page - Local.vi
to be built as part of the System Explorer build with LabVIEW 2021 64-bit.What testing has been done?
Built System Explorer spec on a VM with LabVIEW 2019 and dependencies installed except for EtherCAT. (I had to also remove Action VIs broken by lack of ECAT and cRIO, but these changes will come later when 2021 build support is enabled)