Call System Explorer hardware configuration VIs out of process

[Karl-G1]

• [x] This contribution adheres to CONTRIBUTING.md.

What does this Pull Request accomplish?

This PR builds applications out of the online hardware calls used in the System Explorer configuration code. It then calls them out-of-process by building CLI arguments and handling outputs and errors.

Major Changes

• Applications VI Updates (Revert to Scan Mode.vi, Get HW Config.vi, Check and Download Bitfile.vi)
  • Remove Conditional Disable Structure used in temporary workaround
  • Parse CLI arguments to provide inputs to actual sub VI
  • Write outputs and error to standard output
  • Create build specifications for each application VI
• Create 3 new VIs (Call ...) to wrap the out-of-process calling of "Applications VI"
  • Build array of parameters to call each application
  • Handle standard output and standard error returned by the application
  • Re-save calling VIs to point to these wrappers instead of the application VI
• Two new Sub VIs
  • Build Command Line Arguments.vi
  • Convert inputs (.exe name and array of strings) to full command for SysExec call
  • Build Installed Folder Paths.vi
  • Generates the path to the Custom Device's Applications and data folders from Public Docs
  • This is to avoid building from the VI path inside of an .exe
• Update ECAT FPGA sub VIs to work out-of-process (ECAT FPGA OD FoE.vi, ECAT Wipeback FoE.vi, Host - Revert.vi)
  • Use new sub VI to build path to data folder now that base VI path is in an .exe

Minor Changes

• Update EtherCAT System Tests to call the wrapper VIs to download and revert 9145 bitfile
• Update errors file with new error if Applications cannot be executed
• Remove now unused Conditional Disable Symbol in the project and build.toml

Why should this Pull Request be merged?

Enable building and running Action VIs with hardware configuration calls in LabVIEW 2021 32-bit to be called out-of-process from 64-bit runtime.

What testing has been done?

Tested calling the out-of-process calls with 64-bit VS.

All below testing done with ATS hardware using VS 2019 R3:

• Tested Auto-Detect Modules against PXI with EtherCAT and cRIO
• Used all Action VIs called from ECAT FPGA (UDV) page's buttons:
  • Select/Change FPGA Bitfile
  • Clear Configuration
  • Download FPGA
  • Revert Slave to Scan Mode
• Executed system tests:

[niveristand-diff-bot]

Bleep bloop!

LabVIEW Diff Robot here with some diffs served up hot for your pull request.

Notice something funny? Help fix me on my GitHub repo.

Scan Engine EtherCAT System Tests.lvclass--test 9401 DIO FPGA Mode Loop Back.vi.png


Scan Engine EtherCAT System Tests.lvclass--test 9401 DIO Scan Mode Loop Back.vi.png


SEECD System Explorer.lvlib--Build Command Line Arguments.vi.png


SEECD System Explorer.lvlib--Build Installed Folder Paths.vi.png


SEECD System Explorer.lvlib--Call Check and Download Bitfile.vi.png


SEECD System Explorer.lvlib--Call Get HW Config.vi.png


SEECD System Explorer.lvlib--Call Revert to Scan Mode.vi.png


SEECD System Explorer.lvlib--Check and Download Bitfile.vi.png


SEECD System Explorer.lvlib--ECAT FPGA OD FoE.vi.png


SEECD System Explorer.lvlib--ECAT Wipeback FoE.vi.png


SEECD System Explorer.lvlib--FPGA - Download (ECAT).vi.png

.vi.png)

SEECD System Explorer.lvlib--FPGA - Revert (ECAT).vi.png

.vi.png)

SEECD System Explorer.lvlib--Get HW Config.vi.png


SEECD System Explorer.lvlib--Host - Find Path.vi.png


SEECD System Explorer.lvlib--Host - Revert.vi.png


SEECD System Explorer.lvlib--Main - Auto Detect Modules.vi.png


SEECD System Explorer.lvlib--Revert to Scan Mode.vi.png


[rtzoeller]

Code changes look really good. Only minor feedback:

• [ ] Use Error Cluster from Error Code to create the error messages in the wrapper VIs. It gives more call stack information.

[niveristand-diff-bot]

Bleep bloop!

LabVIEW Diff Robot here with some diffs served up hot for your pull request.

Notice something funny? Help fix me on my GitHub repo.

Scan Engine EtherCAT System Tests.lvclass--test 9401 DIO FPGA Mode Loop Back.vi.png


Scan Engine EtherCAT System Tests.lvclass--test 9401 DIO Scan Mode Loop Back.vi.png


SEECD System Explorer.lvlib--Build Command Line Arguments.vi.png


SEECD System Explorer.lvlib--Build Installed Folder Paths.vi.png


SEECD System Explorer.lvlib--Call Check and Download Bitfile.vi.png


SEECD System Explorer.lvlib--Call Get HW Config.vi.png


SEECD System Explorer.lvlib--Call Revert to Scan Mode.vi.png


SEECD System Explorer.lvlib--Check and Download Bitfile.vi.png


SEECD System Explorer.lvlib--ECAT FPGA OD FoE.vi.png


SEECD System Explorer.lvlib--ECAT Generate OD For FPGA IOV.vi.png


SEECD System Explorer.lvlib--ECAT Wipeback FoE.vi.png


SEECD System Explorer.lvlib--FPGA - Download (ECAT).vi.png

.vi.png)

SEECD System Explorer.lvlib--FPGA - Revert (ECAT).vi.png

.vi.png)

SEECD System Explorer.lvlib--Generate Application Call Error.vi.png


SEECD System Explorer.lvlib--Get HW Config.vi.png


SEECD System Explorer.lvlib--Host - Find Path.vi.png


SEECD System Explorer.lvlib--Host - Revert.vi.png


SEECD System Explorer.lvlib--Main - Auto Detect Modules.vi.png


SEECD System Explorer.lvlib--Revert to Scan Mode.vi.png