Update specialty digital tests with slot config and more efficient loopbacks

[Karl-G1]

• [x] This contribution adheres to CONTRIBUTING.md.

What does this Pull Request accomplish?

Update existing cRIO + 9401 specialty digital system tests:

• Add slot configuration to make sure the 9401s used by the tests are set to Scan Mode
• Clean up test logic and improve stability by using polling reads with longer timeout

Why should this Pull Request be merged?

• When FPGA mode tests are added, the slot configs will need to be set on deployment for these tests to pass.
• The existing test logic is very flaky, as the delays are 0.15-0.25 seconds when writing/reading channel values with the VS API. This is too short, and tests like test Counter.vi frequently fail on ATS runs.

What testing has been done?

Ran the test class ~5 times against the ATS cRIO with VeriStand 2019 R3

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Scan Engine Specialty Digital System Tests.lvclass--Generate Digital Pulse.vi.png


Scan Engine Specialty Digital System Tests.lvclass--test Counter-Driven Output.vi.png


Scan Engine Specialty Digital System Tests.lvclass--test Counter.vi.png


Scan Engine Specialty Digital System Tests.lvclass--test Pulse Width Modulation.vi.png


Scan Engine Specialty Digital System Tests.lvclass--test Quadrature.vi.png


Scan Engine Specialty Digital System Tests.lvclass--Tick Quadrature State.vi.png