Add cRIO FPGA and Hybrid Mode tests

[Karl-G1]

• [x] This contribution adheres to CONTRIBUTING.md.

What does this Pull Request accomplish?

• Add three new system tests for a cRIO 9045 and 3x 9401s:
  • Hybrid (2 FPGA slots and 1 Scan Mode)
  • FPGA (2 FPGA slots)
  • UDV (no C Series IO, only UDVs of various datatypes)
• Add test assets for each test (FPGA VI and LabVIEW Project)

Workaround for Issue #211

When the new tests are run individually, they pass. When run sequentially, LabVIEW RT / VeriStand engine is prone to crashing, which results in various errors.

I filed issue #211 from this failure, and this PR works around the issue for now:

• Add new sub VIs Deploy with Reboot and Retry.vi and Reboot Active Target.vi
• When deploying, reboot the cRIO if the initial deployment fails
• After all tests execute, call reboot from globalSetUp.vi

Why should this Pull Request be merged?

More fully test the ability for the custom device (and VeriStand) to support Combo cRIO targets.

What testing has been done?

Ran the tests against the ATS cRIO.

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cRIO System Tests.lvclass--setUp.vi.png


cRIO System Tests.lvclass--tearDown.vi.png


cRIO System Tests.lvclass--test FPGA DIO.vi.png


cRIO System Tests.lvclass--test FPGA UDVs.vi.png


cRIO System Tests.lvclass--test Hybrid DIO.vi.png


FPGA Main.vi.png


testExample 1.vi.png


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cRIO System Tests.lvclass--setUp.vi.png


cRIO System Tests.lvclass--tearDown.vi.png


cRIO System Tests.lvclass--test FPGA DIO.vi.png


cRIO System Tests.lvclass--test FPGA UDVs.vi.png


cRIO System Tests.lvclass--test Hybrid DIO.vi.png


FPGA Main.vi.png


testExample 1.vi.png


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cRIO System Tests.lvclass--setUp.vi.png


cRIO System Tests.lvclass--tearDown.vi.png


cRIO System Tests.lvclass--test FPGA DIO.vi.png


cRIO System Tests.lvclass--test FPGA UDVs.vi.png


cRIO System Tests.lvclass--test Hybrid DIO.vi.png


FPGA Main.vi.png


testExample 1.vi.png


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cRIO System Tests.lvclass--setUp.vi.png


cRIO System Tests.lvclass--tearDown.vi.png


cRIO System Tests.lvclass--test FPGA DIO.vi.png


cRIO System Tests.lvclass--test FPGA UDVs.vi.png


cRIO System Tests.lvclass--test Hybrid DIO.vi.png


FPGA Main.vi.png


testExample 1.vi.png


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cRIO System Tests.lvclass--Deploy with Reboot and Retry.vi.png


cRIO System Tests.lvclass--globalTearDown.vi.png


cRIO System Tests.lvclass--Reboot Active Target.vi.png


cRIO System Tests.lvclass--setUp.vi.png


cRIO System Tests.lvclass--tearDown.vi.png


cRIO System Tests.lvclass--test FPGA DIO.vi.png


cRIO System Tests.lvclass--test FPGA UDVs.vi.png


cRIO System Tests.lvclass--test Hybrid DIO.vi.png


FPGA Main.vi.png


testExample 1.vi.png


[niveristand-diff-bot]

Bleep bloop!

LabVIEW Diff Robot here with some diffs served up hot for your pull request.

Notice something funny? Help fix me on my GitHub repo.

cRIO System Tests.lvclass--Deploy with Reboot and Retry.vi.png


cRIO System Tests.lvclass--globalTearDown.vi.png


cRIO System Tests.lvclass--Reboot Active Target.vi.png


cRIO System Tests.lvclass--setUp.vi.png


cRIO System Tests.lvclass--tearDown.vi.png


cRIO System Tests.lvclass--test FPGA DIO.vi.png


cRIO System Tests.lvclass--test FPGA UDVs.vi.png


cRIO System Tests.lvclass--test Hybrid DIO.vi.png


FPGA Main.vi.png


testExample 1.vi.png