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nickg / nvc

VHDL compiler and simulator
https://www.nickg.me.uk/nvc/
GNU General Public License v3.0
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fatal: init signal value type does not match signal type #550

Closed avelure closed 2 years ago

avelure commented 2 years ago

This issue is related to initializing a signal with an input port, which requires the relaxed option, but maybe it applies in other cases as well, It was found in uvvm\bitvis_vip_avalon_mm\src\avalon_mm_vvc.vhd

MWE:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package test_pkg is
  type t_avalon_mm_if is record
    reset             : std_logic;
    address           : std_logic_vector;
    begintransfer     : std_logic;
    byte_enable       : std_logic_vector;
    chipselect        : std_logic;
    write             : std_logic;
    writedata         : std_logic_vector;
    read              : std_logic;
    lock              : std_logic;
    readdata          : std_logic_vector;
    response          : std_logic_vector(1 downto 0);
    waitrequest       : std_logic;
    readdatavalid     : std_logic;
    irq               : std_logic;
  end record;
  function init_avalon_mm_if_signals(
    addr_width : natural;
    data_width : natural;
    lock_value : std_logic := '0'
    ) return t_avalon_mm_if;
end package;
package body test_pkg is

  function init_avalon_mm_if_signals(
    addr_width : natural;
    data_width : natural;
    lock_value : std_logic := '0'
    ) return t_avalon_mm_if is
    variable result : t_avalon_mm_if(address(addr_width - 1 downto 0),
                                         byte_enable((data_width/8) - 1 downto 0),
                                         writedata(data_width - 1 downto 0),
                                         readdata(data_width-1 downto 0));
  begin
    result.reset            := '0';
    result.address          := (result.address'range => '0');
    result.begintransfer    := '0';
    result.byte_enable      := (result.byte_enable'range => '1');
    result.chipselect       := '0';
    result.write            := '0';
    result.writedata        := (result.writedata'range => '0');
    result.read             := '0';
    result.lock             := lock_value;
    result.readdata         := (result.readdata'range => 'Z');
    result.response         := (result.response'range => 'Z');
    result.waitrequest      := 'Z';
    result.readdatavalid    := 'Z';
    result.irq              := 'Z';
    return result;
  end function;
end package body;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_pkg.all;

entity test2 is
  generic (
    GC_ADDR_WIDTH                           : integer range 1 to 64 := 8;          -- Avalon MM address bus
    GC_DATA_WIDTH                           : integer range 1 to 64 := 32         -- Avalon MM data bus
    );
  port (
    clk                           : in std_logic;
    avalon_mm_vvc_master_if       : inout t_avalon_mm_if := init_avalon_mm_if_signals(GC_ADDR_WIDTH, GC_DATA_WIDTH)
  );
begin
end entity test2;
architecture beh of test2 is
  signal avalon_mm_vvc_master_if_pd   : t_avalon_mm_if(address(GC_ADDR_WIDTH-1 downto 0),
                                                      byte_enable((GC_DATA_WIDTH/8)-1 downto 0),
                                                      writedata(GC_DATA_WIDTH-1 downto 0),
                                                      readdata(GC_DATA_WIDTH-1 downto 0)) := avalon_mm_vvc_master_if;
begin
end architecture beh;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.test_pkg.all;

entity test is
end entity test;
architecture beh of test is
  signal clk : std_logic;
  signal avalon_mm_if   : t_avalon_mm_if(address(31 downto 0), byte_enable(3 downto 0), writedata(31 downto 0), readdata(31 downto 0));
begin
  i_test : entity work.test2
    generic map(
      GC_ADDR_WIDTH   => 32,
      GC_DATA_WIDTH   => 32
    )
    port map (
      clk => clk,
      avalon_mm_vvc_master_if     => avalon_mm_if
    );

  process
  begin
    report "OK";
    wait;
  end process;

end architecture beh;
nvc --std=08 -a --relaxed test_port_map_interface_3.vhd -e test -r
** Warning: cannot reference signal AVALON_MM_VVC_MASTER_IF during static elaboration
    > test_port_map_interface_3.vhd:82
    |
 82 |                                                       readdata(GC_DATA_WIDTH-1 downto 0)) := avalon_mm_vvc_master_if;
    |                                                                                              ^^^^^^^^^^^^^^^^^^^^^^^
    |
    = Note: the value of a signal is not defined until after the design hierarchy is elaborated
    = Note: the --relaxed option downgrades this to a warning
    = Help: IEEE Std 1076-2008 section 14.4 "Elaboration of a declarative part"

Name       WORK.TEST.I_TEST
Kind       instance
Context    WORK.TEST
Blocks     1
Registers  198
Types      37
  WORK.TEST_PKG.T_AVALON_MM_IF$         {$<0..8>, [*] : $<0..8>, $<0..8>, [*] : $<0..8>, $<0..8>, $<0..8>, [*] : $<0..8>, $<0..8>, $<0..8>, [*] : $<0..8>, $<0..8>, $<0..8>, $<0..8>, $<0..8>}
  WORK.TEST_PKG.T_AVALON_MM_IF          {0..8, [*] : 0..8, 0..8, [*] : 0..8, 0..8, 0..8, [*] : 0..8, 0..8, 0..8, [*] : 0..8, [2] : 0..8, 0..8, 0..8, 0..8}
Variables  5
  GC_ADDR_WIDTH                         // -2^31..2^31-1 => 1..64, constant
  GC_DATA_WIDTH                         // -2^31..2^31-1 => 1..64, constant
  CLK                                   // $<0..8>, signal
  AVALON_MM_VVC_MASTER_IF               // WORK.TEST_PKG.T_AVALON_MM_IF${}, signal
  AVALON_MM_VVC_MASTER_IF_PD            // WORK.TEST_PKG.T_AVALON_MM_IF${} => WORK.TEST_PKG.T_AVALON_MM_IF{}, signal
Begin
   0: r0 := const 32                    // -2^31..2^31-1 => 32
      r1 := const 1                     // -2^31..2^31-1 => 1
      r2 := const 64                    // -2^31..2^31-1 => 64
      r3 := const 0                     // 0..1 => 0
      r4 := debug locus WORK.TEST-BEH+119 // D<>
      r5 := debug locus WORK.TEST2+44   // D<>
      GC_ADDR_WIDTH := store r0
      r6 := debug locus WORK.TEST-BEH+130 // D<>
      r7 := debug locus WORK.TEST2+71   // D<>
      GC_DATA_WIDTH := store r0
      r8 := var upref 1, CLK            // @<$<0..8>> => 0..8
      r9 := load indirect r8            // $<0..8> => 0..8
      r10 := debug locus WORK.TEST2+76  // D<>
      alias signal r9 locus r10
      CLK := store r9
      r11 := link package WORK.TEST_PKG // P<WORK.TEST_PKG>
      r12 := const 0                    // -2^31..2^31-1 => 0
      r13 := const 2147483647           // -2^31..2^31-1 => 2^31-1
      r14 := debug locus WORK.TEST_PKG+126 // D<>
      r15 := debug locus WORK.TEST_PKG+130 // D<>
      r16 := const 2                    // 0..8 => 2
      r17 := const 0                    // 0..8 => 0
      r18 := const 8                    // 0..8 => 8
      r19 := debug locus WORK.TEST_PKG+134 // D<>
      r20 := debug locus WORK.TEST_PKG+138 // D<>
      r21 := fcall WORK.TEST_PKG.INIT_AVALON_MM_IF_SIGNALS(7NATURAL7NATURAL9STD_LOGIC)28WORK.TEST_PKG.T_AVALON_MM_IF r11, r0, r0, r16 // @<WORK.TEST_PKG.T_AVALON_MM_IF{}> => WORK.TEST_PKG.T_AVALON_MM_IF{}
      r22 := const 130                  // # => 130
      r23 := debug locus WORK.TEST.elab+258 // D<>
      push scope locus r23
      r24 := null                       // @<WORK.TEST_PKG.T_AVALON_MM_IF{}>
      r25 := index AVALON_MM_VVC_MASTER_IF // @<WORK.TEST_PKG.T_AVALON_MM_IF${}>
      r26 := record ref r21 field 0     // @<0..8> => 0..8
      r27 := record ref r24 field 0     // @<0..8> => 0..8
      r28 := record ref r25 field 0     // @<$<0..8>> => $<0..8>
      r29 := const 0                    // # => 0
      r30 := const 9                    // # => 9
      r31 := link package IEEE.STD_LOGIC_1164 // P<IEEE.STD_LOGIC_1164>
      r32 := closure IEEE.STD_LOGIC_1164.RESOLVED(Y)U context r31 // C<0..8>
      r33 := resolution wrapper r32 ileft r29 nlits r30 // R<0..8>
      r34 := const 1                    // # => 1
      r35 := load indirect r26          // 0..8
      r36 := debug locus WORK.TEST_PKG+23 // D<>
      r37 := init signal count r34 size r34 value r35 flags r22 locus r36 offset r27 // $<0..8>
      resolve signal r37 resolution r33
      r28 := store indirect r37
      r38 := record ref r21 field 1     // @<[*] : 0..8> => 0..8
      r39 := load indirect r38          // [*] : 0..8 => 0..8
      r40 := null                       // @<0..8>
      r41 := record ref r25 field 1     // @<[*] : $<0..8>> => $<0..8>
      r42 := const 31                   // -2^31..2^31-1 => 31
      r43 := const 1                    // 0..1 => 1
      r44 := null                       // @<#>
      r45 := wrap r44 [r42 r12 r43]     // [*] : # => @<#>
      r46 := debug locus WORK.TEST_PKG+26 // D<>
      r47 := const 32                   // # => 32
      r48 := uarray len r39 dim 0       // #
      length check left r47 == right r48 locus r46
      r49 := unwrap r39                 // @<0..8> => 0..8
      r50 := init signal count r47 size r34 value r49 flags r22 locus r46 offset r40 // $<0..8>
      resolve signal r50 resolution r33
      r51 := wrap r50 [r42 r12 r43]     // [*] : $<0..8>
      r41 := store indirect r51
      r52 := record ref r21 field 2     // @<0..8> => 0..8
      r53 := record ref r24 field 2     // @<0..8> => 0..8
      r54 := record ref r25 field 2     // @<$<0..8>> => $<0..8>
      r55 := load indirect r52          // 0..8
      r56 := debug locus WORK.TEST_PKG+29 // D<>
      r57 := init signal count r34 size r34 value r55 flags r22 locus r56 offset r53 // $<0..8>
      resolve signal r57 resolution r33
      r54 := store indirect r57
      r58 := record ref r21 field 3     // @<[*] : 0..8> => 0..8
      r59 := load indirect r58          // [*] : 0..8 => 0..8
      r60 := record ref r25 field 3     // @<[*] : $<0..8>> => $<0..8>
      r61 := const 3                    // -2^31..2^31-1 => 3
      r62 := wrap r44 [r61 r12 r43]     // [*] : # => @<#>
      r63 := debug locus WORK.TEST_PKG+32 // D<>
      r64 := const 4                    // # => 4
      r65 := uarray len r59 dim 0       // #
      length check left r64 == right r65 locus r63
      r66 := unwrap r59                 // @<0..8> => 0..8
      r67 := init signal count r64 size r34 value r66 flags r22 locus r63 offset r40 // $<0..8>
      resolve signal r67 resolution r33
      r68 := wrap r67 [r61 r12 r43]     // [*] : $<0..8>
      r60 := store indirect r68
      r69 := record ref r21 field 4     // @<0..8> => 0..8
      r70 := record ref r24 field 4     // @<0..8> => 0..8
      r71 := record ref r25 field 4     // @<$<0..8>> => $<0..8>
      r72 := load indirect r69          // 0..8
      r73 := debug locus WORK.TEST_PKG+35 // D<>
      r74 := init signal count r34 size r34 value r72 flags r22 locus r73 offset r70 // $<0..8>
      resolve signal r74 resolution r33
      r71 := store indirect r74
      r75 := record ref r21 field 5     // @<0..8> => 0..8
      r76 := record ref r24 field 5     // @<0..8> => 0..8
      r77 := record ref r25 field 5     // @<$<0..8>> => $<0..8>
      r78 := load indirect r75          // 0..8
      r79 := debug locus WORK.TEST_PKG+38 // D<>
      r80 := init signal count r34 size r34 value r78 flags r22 locus r79 offset r76 // $<0..8>
      resolve signal r80 resolution r33
      r77 := store indirect r80
      r81 := record ref r21 field 6     // @<[*] : 0..8> => 0..8
      r82 := load indirect r81          // [*] : 0..8 => 0..8
      r83 := record ref r25 field 6     // @<[*] : $<0..8>> => $<0..8>
      r84 := debug locus WORK.TEST_PKG+41 // D<>
      r85 := uarray len r82 dim 0       // #
      length check left r47 == right r85 locus r84
      r86 := unwrap r82                 // @<0..8> => 0..8
      r87 := init signal count r47 size r34 value r86 flags r22 locus r84 offset r40 // $<0..8>
      resolve signal r87 resolution r33
      r88 := wrap r87 [r42 r12 r43]     // [*] : $<0..8>
      r83 := store indirect r88
      r89 := record ref r21 field 7     // @<0..8> => 0..8
      r90 := record ref r24 field 7     // @<0..8> => 0..8
      r91 := record ref r25 field 7     // @<$<0..8>> => $<0..8>
      r92 := load indirect r89          // 0..8
      r93 := debug locus WORK.TEST_PKG+44 // D<>
      r94 := init signal count r34 size r34 value r92 flags r22 locus r93 offset r90 // $<0..8>
      resolve signal r94 resolution r33
      r91 := store indirect r94
      r95 := record ref r21 field 8     // @<0..8> => 0..8
      r96 := record ref r24 field 8     // @<0..8> => 0..8
      r97 := record ref r25 field 8     // @<$<0..8>> => $<0..8>
      r98 := load indirect r95          // 0..8
      r99 := debug locus WORK.TEST_PKG+47 // D<>
      r100 := init signal count r34 size r34 value r98 flags r22 locus r99 offset r96 // $<0..8>
      resolve signal r100 resolution r33
      r97 := store indirect r100
      r101 := record ref r21 field 9    // @<[*] : 0..8> => 0..8
      r102 := load indirect r101        // [*] : 0..8 => 0..8
      r103 := record ref r25 field 9    // @<[*] : $<0..8>> => $<0..8>
      r104 := debug locus WORK.TEST_PKG+50 // D<>
      r105 := uarray len r102 dim 0     // #
      length check left r47 == right r105 locus r104
      r106 := unwrap r102               // @<0..8> => 0..8
      r107 := init signal count r47 size r34 value r106 flags r22 locus r104 offset r40 // $<0..8>
      resolve signal r107 resolution r33
      r108 := wrap r107 [r42 r12 r43]   // [*] : $<0..8>
      r103 := store indirect r108
      r109 := record ref r21 field 10   // @<0..8> => 0..8
      r110 := record ref r24 field 10   // @<0..8> => 0..8
      r111 := record ref r25 field 10   // @<$<0..8>> => $<0..8>
      r112 := debug locus WORK.TEST_PKG+71 // D<>
      r113 := const 2                   // # => 2
      r114 := init signal count r113 size r34 value r109 flags r22 locus r112 offset r110 // $<0..8>
      resolve signal r114 resolution r33
      r111 := store indirect r114
      r115 := record ref r21 field 11   // @<0..8> => 0..8
      r116 := record ref r24 field 11   // @<0..8> => 0..8
      r117 := record ref r25 field 11   // @<$<0..8>> => $<0..8>
      r118 := load indirect r115        // 0..8
      r119 := debug locus WORK.TEST_PKG+74 // D<>
      r120 := init signal count r34 size r34 value r118 flags r22 locus r119 offset r116 // $<0..8>
      resolve signal r120 resolution r33
      r117 := store indirect r120
      r121 := record ref r21 field 12   // @<0..8> => 0..8
      r122 := record ref r24 field 12   // @<0..8> => 0..8
      r123 := record ref r25 field 12   // @<$<0..8>> => $<0..8>
      r124 := load indirect r121        // 0..8
      r125 := debug locus WORK.TEST_PKG+77 // D<>
      r126 := init signal count r34 size r34 value r124 flags r22 locus r125 offset r122 // $<0..8>
      resolve signal r126 resolution r33
      r123 := store indirect r126
      r127 := record ref r21 field 13   // @<0..8> => 0..8
      r128 := record ref r24 field 13   // @<0..8> => 0..8
      r129 := record ref r25 field 13   // @<$<0..8>> => $<0..8>
      r130 := load indirect r127        // 0..8
      r131 := debug locus WORK.TEST_PKG+80 // D<>
      r132 := init signal count r34 size r34 value r130 flags r22 locus r131 offset r128 // $<0..8>
      resolve signal r132 resolution r33
      r129 := store indirect r132
      pop scope
      r133 := var upref 1, AVALON_MM_IF // @<WORK.TEST_PKG.T_AVALON_MM_IF${}>
      r134 := record ref r133 field 0   // @<$<0..8>> => $<0..8>
      r135 := load indirect r134        // $<0..8>
      r136 := load indirect r28         // $<0..8>
      map signal r136 to r135 count r34
      r137 := record ref r133 field 1   // @<[*] : $<0..8>> => $<0..8>
      r138 := load indirect r41         // [*] : $<0..8> => $<0..8>
      r139 := uarray len r138 dim 0     // #
      r140 := load indirect r137        // [*] : $<0..8> => $<0..8>
      r141 := load indirect r41         // [*] : $<0..8> => $<0..8>
      r142 := unwrap r141               // $<0..8>
      r143 := unwrap r140               // $<0..8>
      map signal r142 to r143 count r139
      r144 := record ref r133 field 2   // @<$<0..8>> => $<0..8>
      r145 := load indirect r144        // $<0..8>
      r146 := load indirect r54         // $<0..8>
      map signal r146 to r145 count r34
      r147 := record ref r133 field 3   // @<[*] : $<0..8>> => $<0..8>
      r148 := load indirect r60         // [*] : $<0..8> => $<0..8>
      r149 := uarray len r148 dim 0     // #
      r150 := load indirect r147        // [*] : $<0..8> => $<0..8>
      r151 := load indirect r60         // [*] : $<0..8> => $<0..8>
      r152 := unwrap r151               // $<0..8>
      r153 := unwrap r150               // $<0..8>
      map signal r152 to r153 count r149
      r154 := record ref r133 field 4   // @<$<0..8>> => $<0..8>
      r155 := load indirect r154        // $<0..8>
      r156 := load indirect r71         // $<0..8>
      map signal r156 to r155 count r34
      r157 := record ref r133 field 5   // @<$<0..8>> => $<0..8>
      r158 := load indirect r157        // $<0..8>
      r159 := load indirect r77         // $<0..8>
      map signal r159 to r158 count r34
      r160 := record ref r133 field 6   // @<[*] : $<0..8>> => $<0..8>
      r161 := load indirect r83         // [*] : $<0..8> => $<0..8>
      r162 := uarray len r161 dim 0     // #
      r163 := load indirect r160        // [*] : $<0..8> => $<0..8>
      r164 := load indirect r83         // [*] : $<0..8> => $<0..8>
      r165 := unwrap r164               // $<0..8>
      r166 := unwrap r163               // $<0..8>
      map signal r165 to r166 count r162
      r167 := record ref r133 field 7   // @<$<0..8>> => $<0..8>
      r168 := load indirect r167        // $<0..8>
      r169 := load indirect r91         // $<0..8>
      map signal r169 to r168 count r34
      r170 := record ref r133 field 8   // @<$<0..8>> => $<0..8>
      r171 := load indirect r170        // $<0..8>
      r172 := load indirect r97         // $<0..8>
      map signal r172 to r171 count r34
      r173 := record ref r133 field 9   // @<[*] : $<0..8>> => $<0..8>
      r174 := load indirect r103        // [*] : $<0..8> => $<0..8>
      r175 := uarray len r174 dim 0     // #
      r176 := load indirect r173        // [*] : $<0..8> => $<0..8>
      r177 := load indirect r103        // [*] : $<0..8> => $<0..8>
      r178 := unwrap r177               // $<0..8>
      r179 := unwrap r176               // $<0..8>
      map signal r178 to r179 count r175
      r180 := record ref r133 field 10  // @<$<0..8>> => $<0..8>
      r181 := load indirect r180        // $<0..8>
      r182 := load indirect r111        // $<0..8>
      map signal r182 to r181 count r113
      r183 := record ref r133 field 11  // @<$<0..8>> => $<0..8>
      r184 := load indirect r183        // $<0..8>
      r185 := load indirect r117        // $<0..8>
      map signal r185 to r184 count r34
      r186 := record ref r133 field 12  // @<$<0..8>> => $<0..8>
      r187 := load indirect r186        // $<0..8>
      r188 := load indirect r123        // $<0..8>
      map signal r188 to r187 count r34
      r189 := record ref r133 field 13  // @<$<0..8>> => $<0..8>
      r190 := load indirect r189        // $<0..8>
      r191 := load indirect r129        // $<0..8>
      map signal r191 to r190 count r34
      r192 := debug locus WORK.TEST.elab+238 // D<>
      push scope locus r192
      r193 := null                      // @<WORK.TEST_PKG.T_AVALON_MM_IF${}>
      r194 := index AVALON_MM_VVC_MASTER_IF_PD // @<WORK.TEST_PKG.T_AVALON_MM_IF${}>
      r195 := record ref r193 field 0   // @<$<0..8>> => $<0..8>
      r196 := record ref r194 field 0   // @<$<0..8>> => $<0..8>
      r197 := load indirect r28         // $<0..8>
      invalid := init signal count r34 size r34 value r197 flags r29 locus r36 offset r195       <----

** Fatal: init signal value type does not match signal type
[00007FF7338E655A]
[00007FF73395BC26]
[00007FF73394271E]
[00007FF733942F03]
[00007FF73394ADB6]
[00007FF73394DB97]
[00007FF73394DD5B]
[00007FF73394E35B]
[00007FF7338E2BA8]
[00007FF7338E2B1C]
[00007FF7339C6D62] vhpi_put_data+0x23d22
[00007FF7338E13AE]
[00007FF7338E14E6]
[00007FFCC4567034] BaseThreadInitThunk+0x14
[00007FFCC5E626A1] RtlUserThreadStart+0x21
nickg commented 2 years ago

This should be fixed now, could you test again?

avelure commented 2 years ago

Yes, this solves it. Thanks!