nickg / nvc

VHDL compiler and simulator
https://www.nickg.me.uk/nvc/
GNU General Public License v3.0
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Warning on comparing different vector lengths #800

Closed avelure closed 10 months ago

avelure commented 10 months ago

I noticed in #799 I was comparing the wrong vector lengths in the assert in my MWE, would it be possible to add a warning on this? In almost all cases this is a design bug. Modelsim has one (vcom-1083) Implicit array operator "=" always returns FALSE (left length 16 is not equal to right length 8).

nickg commented 10 months ago

Yes it's not hard to add:

** Warning: call to predefined operator "=" always returns FALSE
    > test.vhd:17
    |
 17 |     assert v_default_data(4) = x"43" report to_string(v_default_data(4)) severity failure;
    |            ^^^^^^^^^^^^^^^^^^^^^^^^^ left length is 16 but right length is 8