Another of the same bug: ** Fatal: tree kind T_ALIAS does not have item I_PORTS

[smaslovski]

Hi,

One more case:

$ nvc --std=2008 -a bug.vhd
** Fatal: tree kind T_ALIAS does not have item I_PORTS
    > bug.vhd:12
    |
 12 |   alias logic is std_ulogic;
    |   ^^^^^^^^^^^^^^^^^^^^^^^^^^
[0x55ee2392aa1a] ../src/object.c:215 object_lookup_failed
[0x55ee2392fbe6] ../src/tree.c:576 solve_condition.isra.0.cold
[0x55ee23951f58] ../src/parse.c:6668 p_condition.lto_priv.0
[0x55ee2396357c] ../src/parse.c:9751 p_if_statement
[0x55ee2396357c] ../src/parse.c:10193 p_sequential_statement.lto_priv.0
[0x55ee2395ad3f] ../src/parse.c:7954 p_sequence_of_statements.lto_priv.0
[0x55ee2395c808] ../src/parse.c:8151 p_process_statement_part
[0x55ee2395c808] ../src/parse.c:8213 p_process_statement.lto_priv.0
[0x55ee23969106] ../src/parse.c:12423 p_concurrent_statement.lto_priv.0
[0x55ee2396beee] ../src/parse.c:12490 p_architecture_body
[0x55ee2396beee] ../src/parse.c:12749 p_secondary_unit
[0x55ee2396c707] ../src/parse.c:12775 p_design_unit
[0x55ee2396c707] ../src/parse.c:12889 parse
[0x55ee239a9152] ../src/common.c:2279 analyse_file.part.0
[0x55ee23935ecb] ../src/nvc.c:2273 analyse
[0x55ee23935ecb] ../src/common.c:1874 process_command
[0x55ee23930cae] ../src/nvc.c:2013 main

The content of bug.vhd:

-- types
context fifo_proj is
  library ieee;
  context ieee.ieee_std_context;
  use ieee.numeric_std_unsigned.all;
end context;

library ieee;
context ieee.ieee_std_context;

package fifo_types is
  alias logic is std_ulogic;
  alias logic_vec is std_ulogic_vector;
end package;context work.fifo_proj;
use work.fifo_types.all;

-- fifo
entity fifo is
  generic (constant DEPTH_W : positive := 8);
  port (ireset, irclk, rd_en, iwclk, wr_en : in logic);
end entity;

architecture rtl of fifo is
  signal wr_ptr, rd_ptr : logic_vec (DEPTH_W-1 downto 0);
begin

  write_proc : process (iwclk, ireset) is
  begin
    if ireset then
      wr_ptr <= (others => '0');
    elsif rising_edge(iwclk) then
      if wr_en then
        wr_ptr <= wr_ptr + 1;
      end if;
    end if;
  end process;

  read_proc : process (irclk, ireset) is
  begin
    if ireset then
      rd_ptr  <= (others => '0');
    elsif rising_edge(irclk) then
      if rd_en then
        rd_ptr <= rd_ptr + 1;
      end if;
    end if;
  end process;

end architecture;context work.fifo_proj;

-- testbench
use work.fifo_types.all;
use std.textio.all;

entity tb is
  generic (
    constant T_wclk  : time := 5.0 ns;
    constant T_rclk  : time := 13.1 ns;
    constant DEPTH_W : positive := 8);
end entity;

architecture mixed of tb is
  signal rst, wclk, rclk, wr_req, rd_req : logic := '0';
begin

rst <= '0', '1' after 15 ns, '0' after 36 ns;

wr_clock_gen: process is
begin
  wclk <= '0';
  wait for 0.5*T_wclk;
  wclk <= '1';
  wait for 0.5*T_wclk;
end process;

rd_clock_gen: process is
begin
  rclk <= '0';
  wait for 0.5*T_rclk;
  rclk <= '1';
  wait for 0.5*T_rclk;
end process;

wr_req <= '1';
rd_req <= '1';

FIFO_inst: entity work.fifo(rtl)
  generic map (DEPTH_W => DEPTH_W)
  port map (
    ireset => rst,
    iwclk => wclk, wr_en => wr_req,
    irclk => rclk, rd_en => rd_req
  );

log: postponed process (wclk, rclk) is
  alias s is to_string [logic return string];
  alias s is to_string [logic_vec return string];
  variable l: line;
begin
  swrite(l, "wclk: " & s(wclk) & ", rclk: " & s(rclk) &
            ", wptr: " & s(<< signal .tb.FIFO_inst.wr_ptr : logic_vec (DEPTH_W-1 downto 0) >>) &
            ", rptr: " & s(<< signal .tb.FIFO_inst.rd_ptr : logic_vec (DEPTH_W-1 downto 0) >>)
  );
  writeline(output, l);
end process;

end architecture;

BR, Stanislav