Verilog supply nets

[amb5l]

NVC does not appear to support the supply0 and supply1 net data types. Analysing the following code...

module GND (Y);
output Y;
supply0 Y ;
endmodule

...produces the following error:

** Error: syntax error, unexpected identifier, expecting endmodule
   > D:\devtools\lscc\radiant\2023.1\cae_library\simulation\verilog\iCE40UP\tmp.v:3
   |
 3 | supply0 Y ;
   | ^^^^^^^

[nickg]

The example below is working now:

module GND (Y);
  output Y;
  supply0 Y ;
endmodule // GND

module issue808;
  supply0 gnd;
  supply1 vcc;
  wire    out;

  assign gnd = vcc;

  GND uut (out);

  initial begin
    #1 $display("%x %x %x", gnd, vcc, out);
    $finish;
  end

endmodule // issue808