Closed yikkrubz closed 5 months ago
It seems that guarded blocks are not fully implemented. Although nvc analyses, elaborates and simulates the file gb.vhd, the signal a does not change. It remains 'z'. There are transitions when the design is simulated by ghdl.
nvc --std=08 -a gb.vhd nvc --std=08 -e gb nvc --std=08 -r gb -w --stop-time=40ns
nvc 1.12-devel (1.11.0.r43.g09b76633) (Using LLVM 17.0.6) macos 12.7.2
gb.vhd:
library ieee; use ieee.std_logic_1164.all;
entity gb is end gb;
architecture sim of gb is
signal a : std_logic bus; disconnect a : std_logic after 5 ns; signal b : boolean; signal c : std_logic := '1';
begin
c <= not c after 5 ns;
BL : block (b) is begin a <= guarded c; end block;
process begin wait for 10 ns; b <= true; wait for 20 ns; b <= false; wait; end process;
end architecture;
Guarded blocks and disconnection specifications were only partially implemented before. Should work better now.
It seems that guarded blocks are not fully implemented. Although nvc analyses, elaborates and simulates the file gb.vhd, the signal a does not change. It remains 'z'. There are transitions when the design is simulated by ghdl.
nvc --std=08 -a gb.vhd nvc --std=08 -e gb nvc --std=08 -r gb -w --stop-time=40ns
nvc 1.12-devel (1.11.0.r43.g09b76633) (Using LLVM 17.0.6) macos 12.7.2
gb.vhd:
library ieee; use ieee.std_logic_1164.all;
entity gb is end gb;
architecture sim of gb is
signal a : std_logic bus; disconnect a : std_logic after 5 ns; signal b : boolean; signal c : std_logic := '1';
begin
c <= not c after 5 ns;
BL : block (b) is begin a <= guarded c; end block;
process begin wait for 10 ns; b <= true; wait for 20 ns; b <= false; wait; end process;
end architecture;